From: Peter Zijlstra <peterz@infradead.org>
To: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
linux-mips@linux-mips.org,
Adam Buchbinder <adam.buchbinder@gmail.com>,
Arnd Bergmann <arnd@arndb.de>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
linux-kernel@vger.kernel.org,
"Michael S. Tsirkin" <mst@redhat.com>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>
Subject: Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier
Date: Wed, 31 Aug 2016 13:48:47 +0200 [thread overview]
Message-ID: <20160831114847.GB10153@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1472640279-26593-7-git-send-email-matt.redfearn@imgtec.com>
On Wed, Aug 31, 2016 at 11:44:35AM +0100, Matt Redfearn wrote:
> Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
> architecturally defined ordering barrier. If a CPU does not implement it,
> the arch specifies that it must fall back to SYNC(0).
>
> Define the barrier type and always use it in the pm-cps code rather than
> falling back to the heavyweight sync(0) such that we can benefit from
> the lighter weight sync.
>
Changelog does not explain what 0x10 is, nor why its sufficient for this
case.
Changelog also fails to explain why you do this.
How do you expect anybody to review this?
next prev parent reply other threads:[~2016-08-31 11:49 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-31 10:44 [PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 01/10] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight " Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 11:48 ` Peter Zijlstra [this message]
2016-08-31 13:36 ` Matt Redfearn
2016-08-31 13:36 ` Matt Redfearn
2016-08-31 14:28 ` Peter Zijlstra
2016-08-31 15:49 ` Matt Redfearn
2016-08-31 15:49 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
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