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From: Matt Redfearn <matt.redfearn@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>,
	Matt Redfearn <matt.redfearn@imgtec.com>,
	Adam Buchbinder <adam.buchbinder@gmail.com>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	<linux-kernel@vger.kernel.org>,
	Paul Burton <paul.burton@imgtec.com>,
	Markos Chandras <markos.chandras@imgtec.com>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist
Date: Wed, 31 Aug 2016 11:44:32 +0100	[thread overview]
Message-ID: <1472640279-26593-4-git-send-email-matt.redfearn@imgtec.com> (raw)
In-Reply-To: <1472640279-26593-1-git-send-email-matt.redfearn@imgtec.com>

The check for whether a CPU required the FSB flush workaround
previously required every CPU not requiring it to be whitelisted. That
approach does not scale well as new CPUs are introduced so change the
default from a WARN and returning an error to just returning 0. Any CPUs
requiring the workaround can then be added to the blacklist.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/pm-cps.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 5b31a9405ebc..2faa227a032e 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -272,14 +272,9 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
 		/* On older ones it's unavailable */
 		return -1;
 
-	/* CPUs which do not require the workaround */
-	case CPU_P5600:
-	case CPU_I6400:
-		return 0;
-
 	default:
-		WARN_ONCE(1, "pm-cps: FSB flush unsupported for this CPU\n");
-		return -1;
+		/* Assume that the CPU does not need this workaround */
+		return 0;
 	}
 
 	/*
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: Matt Redfearn <matt.redfearn@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org,
	Matt Redfearn <matt.redfearn@imgtec.com>,
	Adam Buchbinder <adam.buchbinder@gmail.com>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	linux-kernel@vger.kernel.org,
	Paul Burton <paul.burton@imgtec.com>,
	Markos Chandras <markos.chandras@imgtec.com>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist
Date: Wed, 31 Aug 2016 11:44:32 +0100	[thread overview]
Message-ID: <1472640279-26593-4-git-send-email-matt.redfearn@imgtec.com> (raw)
Message-ID: <20160831104432.TxSSphb9OnB3FoHKDK9AZ6JuVyKn2MjnQlLsXkDvVac@z> (raw)
In-Reply-To: <1472640279-26593-1-git-send-email-matt.redfearn@imgtec.com>

The check for whether a CPU required the FSB flush workaround
previously required every CPU not requiring it to be whitelisted. That
approach does not scale well as new CPUs are introduced so change the
default from a WARN and returning an error to just returning 0. Any CPUs
requiring the workaround can then be added to the blacklist.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/pm-cps.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 5b31a9405ebc..2faa227a032e 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -272,14 +272,9 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
 		/* On older ones it's unavailable */
 		return -1;
 
-	/* CPUs which do not require the workaround */
-	case CPU_P5600:
-	case CPU_I6400:
-		return 0;
-
 	default:
-		WARN_ONCE(1, "pm-cps: FSB flush unsupported for this CPU\n");
-		return -1;
+		/* Assume that the CPU does not need this workaround */
+		return 0;
 	}
 
 	/*
-- 
2.7.4

  parent reply	other threads:[~2016-08-31 10:46 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-31 10:44 [PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 01/10] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn [this message]
2016-08-31 10:44   ` [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn
2016-08-31 10:44 ` [PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight " Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 11:48   ` Peter Zijlstra
2016-08-31 13:36     ` Matt Redfearn
2016-08-31 13:36       ` Matt Redfearn
2016-08-31 14:28       ` Peter Zijlstra
2016-08-31 15:49         ` Matt Redfearn
2016-08-31 15:49           ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs Matt Redfearn
2016-08-31 10:44   ` Matt Redfearn

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