* [PATCH v3 00/11] Add Octeon Hotplug CPU Support.
@ 2017-11-14 4:30 Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks Steven J. Hill
` (10 more replies)
0 siblings, 11 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
This patchset adds working Octeon Hotplug CPU. It has been tested
on our 70xx and 78xx develpoment boards. The 70xx has 4 cores and
the 78xx has 48 cores. This was also tested on an EdgerouterPRO,
which has 2 cores.
Changes in v3:
- Reorganized patches to be bisectable.
- Added in suggested changes from v2 patchset.
Chad Reese (1):
MIPS: Add nudges to writes for bit unlocks.
David Daney (4):
MIPS: Allow __cpu_number_map to be larger than NR_CPUS
MIPS: Octeon: Populate kernel memory from cvmx_bootmem named blocks.
MIPS: Add the concept of BOOT_MEM_KERNEL to boot_mem_map.
MIPS: Octeon: Add working hotplug CPU support.
Steven J. Hill (6):
MIPS: Remove unused variable 'lastpfn'
MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
MIPS: Octeon: Header and file cleaning.
MIPS: Octeon: Update values for CVMX_CIU_FUSE register.
MIPS: Octeon: Add Octeon III platforms for console output.
MIPS: Octeon: Remove crufty KEXEC and CRASH_DUMP code.
arch/mips/Kconfig | 14 +-
.../cavium-octeon/executive/cvmx-helper-board.c | 2 +-
.../cavium-octeon/executive/cvmx-helper-jtag.c | 1 +
.../cavium-octeon/executive/cvmx-helper-rgmii.c | 1 +
.../cavium-octeon/executive/cvmx-helper-sgmii.c | 1 +
.../mips/cavium-octeon/executive/cvmx-helper-spi.c | 1 +
.../cavium-octeon/executive/cvmx-helper-xaui.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper.c | 3 +-
arch/mips/cavium-octeon/executive/cvmx-pko.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-spi.c | 11 +-
arch/mips/cavium-octeon/executive/octeon-model.c | 53 ++++-
arch/mips/cavium-octeon/octeon-platform.c | 1 +
arch/mips/cavium-octeon/octeon_boot.h | 95 --------
arch/mips/cavium-octeon/setup.c | 246 +++++++--------------
arch/mips/cavium-octeon/smp.c | 231 +++++++------------
arch/mips/include/asm/bitops.h | 1 +
arch/mips/include/asm/bootinfo.h | 1 +
arch/mips/include/asm/mach-cavium-octeon/irq.h | 8 +
.../asm/mach-cavium-octeon/kernel-entry-init.h | 60 ++++-
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/include/asm/octeon/cvmx-asm.h | 6 +-
arch/mips/include/asm/octeon/cvmx-ciu-defs.h | 26 ++-
arch/mips/include/asm/octeon/cvmx-coremask.h | 26 ++-
arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +-
arch/mips/include/asm/octeon/cvmx-sysinfo.h | 4 +-
arch/mips/include/asm/octeon/cvmx.h | 40 ++--
arch/mips/include/asm/octeon/octeon.h | 2 +
arch/mips/include/asm/smp.h | 2 +-
arch/mips/kernel/setup.c | 30 ++-
arch/mips/kernel/smp.c | 2 +-
arch/mips/mm/init.c | 4 -
arch/mips/pci/pcie-octeon.c | 12 +-
32 files changed, 410 insertions(+), 481 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/octeon_boot.h
--
2.1.4
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 15:39 ` Ralf Baechle
2017-11-14 4:30 ` [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn' Steven J. Hill
` (9 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Chad Reese, ralf, David Daney
From: Chad Reese <kreese@caviumnetworks.com>
Flushing the writes lets other CPUs waiting for the lock to get it
sooner.
Signed-off-by: Chad Reese <kreese@caviumnetworks.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
---
arch/mips/include/asm/bitops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index fa57cef..da1b871 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -456,6 +456,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
{
smp_mb__before_llsc();
__clear_bit(nr, addr);
+ nudge_writes();
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn'
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 15:40 ` Ralf Baechle
2017-11-14 4:30 ` [PATCH v3 03/11] MIPS: Allow __cpu_number_map to be larger than NR_CPUS Steven J. Hill
` (8 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
'lastpfn' is never used for anything. Remove it.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com
---
arch/mips/mm/init.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 5f6ea7d..84b7b59 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -402,7 +402,6 @@ int page_is_ram(unsigned long pagenr)
void __init paging_init(void)
{
unsigned long max_zone_pfns[MAX_NR_ZONES];
- unsigned long lastpfn __maybe_unused;
pagetable_init();
@@ -416,17 +415,14 @@ void __init paging_init(void)
max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
#endif
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
- lastpfn = max_low_pfn;
#ifdef CONFIG_HIGHMEM
max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
- lastpfn = highend_pfn;
if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
printk(KERN_WARNING "This processor doesn't support highmem."
" %ldk highmem ignored\n",
(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
- lastpfn = max_low_pfn;
}
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 03/11] MIPS: Allow __cpu_number_map to be larger than NR_CPUS
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn' Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere Steven J. Hill
` (7 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, ralf, Carlos Munoz
From: David Daney <david.daney@cavium.com>
In systems where the CPU id space is sparse, this allows a smaller
NR_CPUS to be chosen, thus keeping internal data structures smaller.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Carlos Munoz <cmunoz@caviumnetworks.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
---
arch/mips/Kconfig | 12 +++++++++++-
arch/mips/include/asm/smp.h | 2 +-
arch/mips/kernel/smp.c | 2 +-
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5d3284d..475239d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -916,7 +916,8 @@ config CAVIUM_OCTEON_SOC
select USE_OF
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_SMP
- select NR_CPUS_DEFAULT_16
+ select NR_CPUS_DEFAULT_64
+ select MIPS_NR_CPU_NR_MAP_1024
select BUILTIN_DTB
select MTD_COMPLEX_MAPPINGS
select SYS_SUPPORTS_RELOCATABLE
@@ -2726,6 +2727,15 @@ config NR_CPUS
config MIPS_PERF_SHARED_TC_COUNTERS
bool
+config MIPS_NR_CPU_NR_MAP_1024
+ bool
+
+config MIPS_NR_CPU_NR_MAP
+ int
+ depends on SMP
+ default 1024 if MIPS_NR_CPU_NR_MAP_1024
+ default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
+
#
# Timer Interrupt Frequency Configuration
#
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 9e494f8..88ebd83 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -29,7 +29,7 @@ extern cpumask_t cpu_foreign_map[];
/* Map from cpu id to sequential logical cpu number. This will only
not be idempotent when cpus failed to come on-line. */
-extern int __cpu_number_map[NR_CPUS];
+extern int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP];
#define cpu_number_map(cpu) __cpu_number_map[cpu]
/* The reverse map from sequential logical cpu number to cpu id. */
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 88be966..d84b906 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -48,7 +48,7 @@
#include <asm/setup.h>
#include <asm/maar.h>
-int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
+int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
EXPORT_SYMBOL(__cpu_number_map);
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (2 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 03/11] MIPS: Allow __cpu_number_map to be larger than NR_CPUS Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 19:08 ` Ralf Baechle
2017-11-27 18:56 ` David Daney
2017-11-14 4:30 ` [PATCH v3 05/11] MIPS: Octeon: Header and file cleaning Steven J. Hill
` (6 subsequent siblings)
10 siblings, 2 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
---
arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
arch/mips/pci/pcie-octeon.c | 12 ++++++------
5 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index f24be0b..75108ec 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -862,7 +862,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
*/
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
- cvmx_wait(100000000ull);
+ __delay(100000000ull);
for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
retry_cnt = 100000;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index 459e3b1..f51957a 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -215,7 +215,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
spxx_clk_ctl.u64 = 0;
spxx_clk_ctl.s.runbist = 1;
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
- cvmx_wait(10 * MS);
+ __delay(10 * MS);
spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
if (spxx_bist_stat.s.stat0)
cvmx_dprintf
@@ -265,14 +265,14 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
spxx_clk_ctl.s.rcvtrn = 0;
spxx_clk_ctl.s.srxdlck = 0;
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
- cvmx_wait(100 * MS);
+ __delay(100 * MS);
/* Reset SRX0 DLL */
spxx_clk_ctl.s.srxdlck = 1;
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
/* Waiting for Inf0 Spi4 RX DLL to lock */
- cvmx_wait(100 * MS);
+ __delay(100 * MS);
/* Enable dynamic alignment */
spxx_trn4_ctl.s.trntest = 0;
@@ -527,7 +527,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
spxx_clk_ctl.s.rcvtrn = 1;
spxx_clk_ctl.s.srxdlck = 1;
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
- cvmx_wait(1000 * MS);
+ __delay(1000 * MS);
/* SRX0 clear the boot bit */
spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
@@ -536,7 +536,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
/* Wait for the training sequence to complete */
cvmx_dprintf("SPI%d: Waiting for training\n", interface);
- cvmx_wait(1000 * MS);
+ __delay(1000 * MS);
/* Wait a really long time here */
timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
/*
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index c00501d..29ae636 100644
--- a/arch/mips/include/asm/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -36,6 +36,8 @@
#ifndef __CVMX_FPA_H__
#define __CVMX_FPA_H__
+#include <linux/delay.h>
+
#include <asm/octeon/cvmx-address.h>
#include <asm/octeon/cvmx-fpa-defs.h>
@@ -165,7 +167,7 @@ static inline void cvmx_fpa_enable(void)
}
/* Enforce a 10 cycle delay between config and enable */
- cvmx_wait(10);
+ __delay(10);
}
/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 205ab2c..25854ab 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -30,6 +30,7 @@
#include <linux/kernel.h>
#include <linux/string.h>
+#include <linux/delay.h>
enum cvmx_mips_space {
CVMX_MIPS_SPACE_XKSEG = 3LL,
@@ -429,18 +430,6 @@ static inline uint64_t cvmx_get_cycle(void)
}
/**
- * Wait for the specified number of cycle
- *
- */
-static inline void cvmx_wait(uint64_t cycles)
-{
- uint64_t done = cvmx_get_cycle() + cycles;
-
- while (cvmx_get_cycle() < done)
- ; /* Spin */
-}
-
-/**
* Reads a chip global cycle counter. This counts CPU cycles since
* chip reset. The counter is 64 bit.
* This register does not exist on CN38XX pass 1 silicion
@@ -481,7 +470,7 @@ static inline uint64_t cvmx_get_cycle_global(void)
result = -1; \
break; \
} else \
- cvmx_wait(100); \
+ __delay(100); \
} \
} while (0); \
result; \
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index fd28874..87ba86b 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
return -1;
}
- cvmx_wait(10000);
+ __delay(10000);
pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
} while (pciercx_cfg032.s.dlla == 0);
@@ -821,7 +821,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
* don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
* fixed number of cycles.
*/
- cvmx_wait(400000);
+ __delay(400000);
/*
* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
@@ -1018,7 +1018,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
i = in_p_offset;
while (i--) {
cvmx_write64_uint32(write_address, 0);
- cvmx_wait(10000);
+ __delay(10000);
}
/*
@@ -1034,7 +1034,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
old_in_fif_p_count = dbg_data.s.data & 0xff;
cvmx_write64_uint32(write_address, 0);
- cvmx_wait(10000);
+ __delay(10000);
dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
in_fif_p_count = dbg_data.s.data & 0xff;
} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
@@ -1053,7 +1053,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
while (in_fif_p_count != 0) {
cvmx_write64_uint32(write_address, 0);
- cvmx_wait(10000);
+ __delay(10000);
in_fif_p_count = (in_fif_p_count + 1) & 0xff;
}
/*
@@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
do {
if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
return -1;
- cvmx_wait(10000);
+ __delay(10000);
pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
} while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 05/11] MIPS: Octeon: Header and file cleaning.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (3 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 06/11] MIPS: Octeon: Update values for CVMX_CIU_FUSE register Steven J. Hill
` (5 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
In preparation for new hotplug CPU, some housekeeping:
* Clean-up header file dependencies, specifically move inclusion
of some headers to only the files that need them.
* Clean-ups from checkpatch in arch/mips/cavium-octeon/setup.c
* Add defining of NR_IRQS_LEGACY for completeness.
* Move CVMX_TMP_STR macros from top level to cvmx-asm.h
* Update some copyright dates.
* Add some missing register include files to top level.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
---
arch/mips/cavium-octeon/executive/cvmx-helper-board.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper-spi.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-pko.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-spi.c | 1 +
arch/mips/cavium-octeon/octeon-platform.c | 1 +
arch/mips/cavium-octeon/setup.c | 10 +++++++++-
arch/mips/cavium-octeon/smp.c | 1 +
arch/mips/include/asm/mach-cavium-octeon/irq.h | 8 ++++++++
arch/mips/include/asm/octeon/cvmx-asm.h | 6 ++++--
arch/mips/include/asm/octeon/cvmx-sysinfo.h | 4 ++--
arch/mips/include/asm/octeon/cvmx.h | 10 +++-------
16 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index ab8362e..22d46fe 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -32,7 +32,7 @@
*/
#include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-bootinfo.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
index 607b4e6..e417037 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -33,6 +33,7 @@
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-helper-jtag.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index d18ed5a..2d84490 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -30,6 +30,7 @@
* and monitoring.
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 5782833..a25275d 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -31,6 +31,7 @@
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
index ef16aa0..d9dac21 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -34,6 +34,7 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
* and monitoring.
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-spi.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index 19d54e0..d692638 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -32,6 +32,7 @@
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index 75108ec..1e807f8 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -31,6 +31,7 @@
*
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index 676fab5..ec5b013 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -30,6 +30,7 @@
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-pko.h>
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index f51957a..d346ea7 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -30,6 +30,7 @@
* Support library for the SPI
*/
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/cvmx-config.h>
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 8505db4..a605191 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -13,6 +13,7 @@
#include <linux/libfdt.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-bootinfo.h>
#include <asm/octeon/cvmx-helper-board.h>
#ifdef CONFIG_USB
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0..2085138 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -39,6 +39,7 @@
#include <asm/time.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-rst-defs.h>
@@ -165,6 +166,7 @@ static int octeon_kexec_prepare(struct kimage *image)
int argc = 0, offt;
char *str = (char *)image->segment[i].buf;
char *ptr = strchr(str, ' ');
+
while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
*ptr = '\0';
if (ptr[1] != ' ') {
@@ -357,6 +359,7 @@ void octeon_write_lcd(const char *s)
ioremap_nocache(octeon_bootinfo->led_display_base_addr,
8);
int i;
+
for (i = 0; i < 8; i++, s++) {
if (*s)
iowrite8(*s, lcd_address + i);
@@ -429,6 +432,7 @@ static void octeon_restart(char *command)
/* Disable all watchdogs before soft reset. They don't get cleared */
#ifdef CONFIG_SMP
int cpu;
+
for_each_online_cpu(cpu)
cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
#else
@@ -715,11 +719,13 @@ void __init prom_init(void)
if (OCTEON_IS_OCTEON2()) {
/* I/O clock runs at a different rate than the CPU. */
union cvmx_mio_rst_boot rst_boot;
+
rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
} else if (OCTEON_IS_OCTEON3()) {
/* I/O clock runs at a different rate than the CPU. */
union cvmx_rst_boot rst_boot;
+
rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
} else {
@@ -927,6 +933,7 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
{
if (addr > *mem && addr < *mem + *size) {
u64 inc = addr - *mem;
+
add_memory_region(*mem, inc, BOOT_MEM_RAM);
*mem += inc;
*size -= inc;
@@ -947,6 +954,7 @@ void __init fw_init_cmdline(void)
for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
const char *arg =
cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
+
if (strlen(arcs_cmdline) + strlen(arg) + 1 <
sizeof(arcs_cmdline) - 1) {
strcat(arcs_cmdline, " ");
@@ -1202,7 +1210,7 @@ void __init device_tree_init(void)
init_octeon_system_type();
}
-static int __initdata disable_octeon_edac_p;
+static int disable_octeon_edac_p __initdata;
static int __init disable_octeon_edac(char *str)
{
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 75e7c86..f08f175 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -21,6 +21,7 @@
#include <asm/setup.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-sysinfo.h>
#include "octeon_boot.h"
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 64b86b9..7c2bf76 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -11,6 +11,14 @@
#define NR_IRQS OCTEON_IRQ_LAST
#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
+/*
+ * 0 - unused.
+ * 1..8 - MIPS
+ *
+ * For a total of 9
+ */
+#define NR_IRQS_LEGACY 9
+
enum octeon_irq {
/* 1 - 8 represent the 8 MIPS standard interrupt sources */
OCTEON_IRQ_SW0 = 1,
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
index 31eacc2..0c6ae93 100644
--- a/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2017 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -32,7 +32,9 @@
#ifndef __CVMX_ASM_H__
#define __CVMX_ASM_H__
-#include <asm/octeon/octeon-model.h>
+/* turn the variable name into a string */
+#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
+#define CVMX_TMP_STR2(x) #x
/* other useful stuff */
#define CVMX_SYNC asm volatile ("sync" : : : "memory")
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
index c6c3ee3..ea1381a 100644
--- a/arch/mips/include/asm/octeon/cvmx-sysinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2016 Cavium, Inc.
+ * Copyright (c) 2003-2017 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -32,7 +32,7 @@
#ifndef __CVMX_SYSINFO_H__
#define __CVMX_SYSINFO_H__
-#include "cvmx-coremask.h"
+#include <asm/octeon/cvmx-bootinfo.h>
#define OCTEON_SERIAL_LEN 20
/**
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 25854ab..392556a 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -54,8 +54,7 @@ enum cvmx_mips_space {
#endif
#include <asm/octeon/cvmx-asm.h>
-#include <asm/octeon/cvmx-packet.h>
-#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/octeon-model.h>
#include <asm/octeon/cvmx-ciu-defs.h>
#include <asm/octeon/cvmx-ciu3-defs.h>
@@ -68,8 +67,9 @@ enum cvmx_mips_space {
#include <asm/octeon/cvmx-led-defs.h>
#include <asm/octeon/cvmx-mio-defs.h>
#include <asm/octeon/cvmx-pow-defs.h>
+#include <asm/octeon/cvmx-rst-defs.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
-#include <asm/octeon/cvmx-bootinfo.h>
#include <asm/octeon/cvmx-bootmem.h>
#include <asm/octeon/cvmx-l2c.h>
@@ -102,10 +102,6 @@ static inline uint32_t cvmx_get_proc_id(void)
return id;
}
-/* turn the variable name into a string */
-#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
-#define CVMX_TMP_STR2(x) #x
-
/**
* Builds a bit mask given the required size in bits.
*
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 06/11] MIPS: Octeon: Update values for CVMX_CIU_FUSE register.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (4 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 05/11] MIPS: Octeon: Header and file cleaning Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 07/11] MIPS: Octeon: Add Octeon III platforms for console output Steven J. Hill
` (4 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
Values for the CVMX_CIU_FUSE register incorrect for some platforms.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
---
arch/mips/include/asm/octeon/cvmx-ciu-defs.h | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index 6e61792..8947d88 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -43,7 +43,31 @@
#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_FUSE CVMX_CIU_FUSE_FUNC()
+static inline uint64_t CVMX_CIU_FUSE_FUNC(void)
+{
+ switch (cvmx_get_octeon_family() & OCTEON_FAMILY_MASK) {
+ case OCTEON_CN30XX:
+ case OCTEON_CN31XX:
+ case OCTEON_CN38XX:
+ case OCTEON_CN50XX:
+ case OCTEON_CN52XX:
+ case OCTEON_CN56XX:
+ case OCTEON_CN58XX:
+ case OCTEON_CN61XX:
+ case OCTEON_CN63XX:
+ case OCTEON_CN66XX:
+ case OCTEON_CN68XX:
+ case OCTEON_CN70XX:
+ case OCTEON_CNF71XX:
+ default:
+ return CVMX_ADD_IO_SEG(0x0001070000000728ull);
+ case OCTEON_CN73XX:
+ case OCTEON_CN78XX:
+ case OCTEON_CNF75XX:
+ return CVMX_ADD_IO_SEG(0x00010100000001A0ull);
+ }
+}
#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 07/11] MIPS: Octeon: Add Octeon III platforms for console output.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (5 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 06/11] MIPS: Octeon: Update values for CVMX_CIU_FUSE register Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 08/11] MIPS: Octeon: Remove crufty KEXEC and CRASH_DUMP code Steven J. Hill
` (3 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
Support Octeon III platforms when printing out the model and
SoC information during boot.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
---
arch/mips/cavium-octeon/executive/octeon-model.c | 53 ++++++++++++++++++++++--
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index 3410523..069a996 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -67,7 +67,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
union cvmx_mio_fus_dat2 fus_dat2;
union cvmx_mio_fus_dat3 fus_dat3;
char fuse_model[10];
- uint32_t fuse_data = 0;
+ uint64_t fuse_data = 0;
uint64_t l2d_fus3 = 0;
if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
@@ -453,11 +453,13 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
}
clock_mhz = octeon_get_clock_rate() / 1000000;
- if (family[0] != '3') {
+ if (family[0] != '3')
+ goto out;
+
+ if (OCTEON_IS_OCTEON1PLUS() || OCTEON_IS_OCTEON2()) {
int fuse_base = 384 / 8;
if (family[0] == '6')
fuse_base = 832 / 8;
-
/* Check for model in fuses, overrides normal decode */
/* This is _not_ valid for Octeon CN3XXX models */
fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
@@ -486,7 +488,52 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
family = fuse_model;
}
}
+ } else {
+ /* Format for Octeon 3. */
+ fuse_data = cvmx_read_csr(CVMX_MIO_FUS_PDF);
+ if (fuse_data & ((1ULL << 48) - 1)) {
+ char suffix_str[4] = {0};
+ char fuse_suffix[4] = {0};
+ int i;
+ int model = fuse_data & ((1ULL << 17) - 1);
+ int suf_bits = (fuse_data >> 17) & ((1ULL << 15) - 1);
+ for (i = 0; i < 3; i++) {
+ /* A-Z are encoded 1-26, 27-31 are
+ reserved values. */
+ if ((suf_bits & 0x1f) && (suf_bits & 0x1f) <= 26)
+ suffix_str[i] = 'A' + (suf_bits & 0x1f) - 1;
+ suf_bits = suf_bits >> 5;
+ }
+ if (strlen(suffix_str) && model) { /* Have both number and suffix in fuses, so both */
+ sprintf(fuse_model, "%d%s", model, suffix_str);
+ core_model = "";
+ family = fuse_model;
+ } else if (strlen(suffix_str) && !model) { /* Only have suffix, so add suffix to 'normal' model number */
+ sprintf(fuse_model, "%s%s", core_model, suffix_str);
+ core_model = fuse_model;
+ } else if (model) { /* Don't have suffix, so just use model from fuses */
+ sprintf(fuse_model, "%d", model);
+ core_model = "";
+ family = fuse_model;
+ }
+ /* in case of invalid model suffix bits
+ only set, we do nothing. */
+
+ /* Check to see if we have a custom type
+ suffix. */
+ suf_bits = (fuse_data >> 33) & ((1ULL << 15) - 1);
+ for (i = 0; i < 3; i++) {
+ /* A-Z are encoded 1-26, 27-31 are
+ reserved values. */
+ if ((suf_bits & 0x1f) && (suf_bits & 0x1f) <= 26)
+ fuse_suffix[i] = 'A' + (suf_bits & 0x1f) - 1;
+ suf_bits = suf_bits >> 5;
+ }
+ if (strlen(fuse_suffix))
+ suffix = fuse_suffix;
+ }
}
+out:
sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
return buffer;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 08/11] MIPS: Octeon: Remove crufty KEXEC and CRASH_DUMP code.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (6 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 07/11] MIPS: Octeon: Add Octeon III platforms for console output Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 09/11] MIPS: Octeon: Populate kernel memory from cvmx_bootmem named blocks Steven J. Hill
` (2 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <Steven.Hill@cavium.com>
Get rid of obsolete KEXEC and CRASH_DUMP code. This is to
prepare for adding in the new hotplug CPU code.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
---
arch/mips/cavium-octeon/setup.c | 168 ++--------------------------------------
1 file changed, 7 insertions(+), 161 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2085138..46e2bb0 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -100,56 +100,6 @@ static void octeon_kexec_smp_down(void *ignored)
}
#endif
-#define OCTEON_DDR0_BASE (0x0ULL)
-#define OCTEON_DDR0_SIZE (0x010000000ULL)
-#define OCTEON_DDR1_BASE (0x410000000ULL)
-#define OCTEON_DDR1_SIZE (0x010000000ULL)
-#define OCTEON_DDR2_BASE (0x020000000ULL)
-#define OCTEON_DDR2_SIZE (0x3e0000000ULL)
-#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
-
-static struct kimage *kimage_ptr;
-
-static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
-{
- int64_t addr;
- struct cvmx_bootmem_desc *bootmem_desc;
-
- bootmem_desc = cvmx_bootmem_get_desc();
-
- if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
- mem_size = OCTEON_MAX_PHY_MEM_SIZE;
- pr_err("Error: requested memory too large,"
- "truncating to maximum size\n");
- }
-
- bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
- bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
-
- addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
- bootmem_desc->head_addr = 0;
-
- if (mem_size <= OCTEON_DDR0_SIZE) {
- __cvmx_bootmem_phy_free(addr,
- mem_size - reserve_low_mem -
- low_reserved_bytes, 0);
- return;
- }
-
- __cvmx_bootmem_phy_free(addr,
- OCTEON_DDR0_SIZE - reserve_low_mem -
- low_reserved_bytes, 0);
-
- mem_size -= OCTEON_DDR0_SIZE;
-
- if (mem_size > OCTEON_DDR1_SIZE) {
- __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
- __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
- mem_size - OCTEON_DDR1_SIZE, 0);
- } else
- __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
-}
-
static int octeon_kexec_prepare(struct kimage *image)
{
int i;
@@ -181,72 +131,23 @@ static int octeon_kexec_prepare(struct kimage *image)
break;
}
}
-
- /*
- * Information about segments will be needed during pre-boot memory
- * initialization.
- */
- kimage_ptr = image;
return 0;
}
static void octeon_generic_shutdown(void)
{
- int i;
#ifdef CONFIG_SMP
int cpu;
-#endif
- struct cvmx_bootmem_desc *bootmem_desc;
- void *named_block_array_ptr;
- bootmem_desc = cvmx_bootmem_get_desc();
- named_block_array_ptr =
- cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
-
-#ifdef CONFIG_SMP
+ secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
+ secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
/* disable watchdogs */
for_each_online_cpu(cpu)
cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
#else
cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
-#endif
- if (kimage_ptr != kexec_crash_image) {
- memset(named_block_array_ptr,
- 0x0,
- CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
- sizeof(struct cvmx_bootmem_named_block_desc));
- /*
- * Mark all memory (except low 0x100000 bytes) as free.
- * It is the same thing that bootloader does.
- */
- kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
- 0x100000);
- /*
- * Allocate all segments to avoid their corruption during boot.
- */
- for (i = 0; i < kimage_ptr->nr_segments; i++)
- cvmx_bootmem_alloc_address(
- kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
- kimage_ptr->segment[i].mem - PAGE_SIZE,
- PAGE_SIZE);
- } else {
- /*
- * Do not mark all memory as free. Free only named sections
- * leaving the rest of memory unchanged.
- */
- struct cvmx_bootmem_named_block_desc *ptr =
- (struct cvmx_bootmem_named_block_desc *)
- named_block_array_ptr;
-
- for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
- if (ptr[i].size)
- cvmx_bootmem_free_named(ptr[i].name);
- }
kexec_args[2] = 1UL; /* running on octeon_main_processor */
kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
-#ifdef CONFIG_SMP
- secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
- secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
#endif
}
@@ -928,7 +829,6 @@ void __init prom_init(void)
}
/* Exclude a single page from the regions obtained in plat_mem_setup. */
-#ifndef CONFIG_CRASH_DUMP
static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
{
if (addr > *mem && addr < *mem + *size) {
@@ -944,7 +844,6 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
*size -= PAGE_SIZE;
}
}
-#endif /* CONFIG_CRASH_DUMP */
void __init fw_init_cmdline(void)
{
@@ -975,11 +874,7 @@ void __init plat_mem_setup(void)
uint64_t mem_alloc_size;
uint64_t total;
uint64_t crashk_end;
-#ifndef CONFIG_CRASH_DUMP
int64_t memory;
- uint64_t kernel_start;
- uint64_t kernel_size;
-#endif
total = 0;
crashk_end = 0;
@@ -1020,9 +915,6 @@ void __init plat_mem_setup(void)
CVMX_BOOTMEM_FLAG_NO_LOCKING);
if (memory >= 0) {
u64 size = mem_alloc_size;
-#ifdef CONFIG_KEXEC
- uint64_t end;
-#endif
/*
* exclude a page at the beginning and end of
@@ -1035,66 +927,20 @@ void __init plat_mem_setup(void)
memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
CVMX_PCIE_BAR1_PHYS_SIZE,
&memory, &size);
-#ifdef CONFIG_KEXEC
- end = memory + mem_alloc_size;
/*
- * This function automatically merges address regions
- * next to each other if they are received in
- * incrementing order
+ * This function automatically merges address
+ * regions next to each other if they are
+ * received in incrementing order.
*/
- if (memory < crashk_base && end > crashk_end) {
- /* region is fully in */
- add_memory_region(memory,
- crashk_base - memory,
- BOOT_MEM_RAM);
- total += crashk_base - memory;
- add_memory_region(crashk_end,
- end - crashk_end,
- BOOT_MEM_RAM);
- total += end - crashk_end;
- continue;
- }
-
- if (memory >= crashk_base && end <= crashk_end)
- /*
- * Entire memory region is within the new
- * kernel's memory, ignore it.
- */
- continue;
-
- if (memory > crashk_base && memory < crashk_end &&
- end > crashk_end) {
- /*
- * Overlap with the beginning of the region,
- * reserve the beginning.
- */
- mem_alloc_size -= crashk_end - memory;
- memory = crashk_end;
- } else if (memory < crashk_base && end > crashk_base &&
- end < crashk_end)
- /*
- * Overlap with the beginning of the region,
- * chop of end.
- */
- mem_alloc_size -= end - crashk_base;
-#endif
- add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+ if (size)
+ add_memory_region(memory, size, BOOT_MEM_RAM);
total += mem_alloc_size;
- /* Recovering mem_alloc_size */
- mem_alloc_size = 4 << 20;
} else {
break;
}
}
cvmx_bootmem_unlock();
- /* Add the memory region for the kernel. */
- kernel_start = (unsigned long) _text;
- kernel_size = _end - _text;
-
- /* Adjust for physical offset. */
- kernel_start &= ~0xffffffff80000000ULL;
- add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
#endif /* CONFIG_CRASH_DUMP */
#ifdef CONFIG_CAVIUM_RESERVE32
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 09/11] MIPS: Octeon: Populate kernel memory from cvmx_bootmem named blocks.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (7 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 08/11] MIPS: Octeon: Remove crufty KEXEC and CRASH_DUMP code Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 10/11] MIPS: Add the concept of BOOT_MEM_KERNEL to boot_mem_map Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 11/11] MIPS: Octeon: Add working hotplug CPU support Steven J. Hill
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, ralf, Carlos Munoz, Corey Minyard
From: David Daney <david.daney@cavium.com>
Command line syntax is:
mem=block:block_name1,block_name2,...
A maximum of 4 blocks are currently supported
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Carlos Munoz <carlos.munoz@caviumnetworks.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
---
arch/mips/cavium-octeon/setup.c | 66 ++++++++++++++++++++++++++++++++++++-----
1 file changed, 59 insertions(+), 7 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 46e2bb0..2855d8d 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -198,6 +198,9 @@ static int octeon_uart;
extern asmlinkage void handle_int(void);
+/* Up to four blocks may be specified. */
+static char __initdata named_memory_blocks[4][CVMX_BOOTMEM_NAME_LEN];
+
/**
* Return non zero if we are currently running in the Octeon simulator
*
@@ -774,7 +777,26 @@ void __init prom_init(void)
for (i = 0; i < argc; i++) {
const char *arg =
cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
- if ((strncmp(arg, "MEM=", 4) == 0) ||
+ if (strncmp(arg, "mem=block:", 10) == 0) {
+ const char *pos = arg + 10;
+ int j;
+
+ for (j = 0; pos[0] && j < ARRAY_SIZE(named_memory_blocks); j++) {
+ int len;
+ char *comma = strchr(pos, ',');
+ if (comma)
+ len = comma - pos;
+ else
+ len = max(strlen(pos), ARRAY_SIZE(named_memory_blocks[0]));
+ strncpy(named_memory_blocks[j], pos, len);
+ if (comma)
+ pos = comma + 1;
+ else
+ break;
+ }
+ for (j = 0; j < ARRAY_SIZE(named_memory_blocks); j++)
+ pr_err("Named Block[%d] = \"%s\"\n", j, named_memory_blocks[j]);
+ } else if ((strncmp(arg, "MEM=", 4) == 0) ||
(strncmp(arg, "mem=", 4) == 0)) {
max_memory = memparse(arg + 4, &p);
if (max_memory == 0)
@@ -875,10 +897,35 @@ void __init plat_mem_setup(void)
uint64_t total;
uint64_t crashk_end;
int64_t memory;
+ const struct cvmx_bootmem_named_block_desc *named_block;
total = 0;
crashk_end = 0;
+ if (named_memory_blocks[0][0]) {
+ /* Memory from named blocks only */
+ int i;
+
+ for (i = 0;
+ named_memory_blocks[i][0] && i < ARRAY_SIZE(named_memory_blocks);
+ i++) {
+ named_block = cvmx_bootmem_find_named_block(named_memory_blocks[i]);
+ if (!named_block) {
+ pr_err("Error: Couldn't find cvmx_bootmem block \"%s\"",
+ named_memory_blocks[i]);
+ return;
+ }
+ pr_info("Adding memory from \"%s\": %016lx @ %016lx\n",
+ named_memory_blocks[i],
+ (unsigned long)named_block->size,
+ (unsigned long)named_block->base_addr);
+ add_memory_region(named_block->base_addr, named_block->size,
+ BOOT_MEM_RAM);
+ total += named_block->size;
+ }
+ goto mem_alloc_done;
+ }
+
/*
* The Mips memory init uses the first memory location for
* some memory vectors. When SPARSEMEM is in use, it doesn't
@@ -901,18 +948,23 @@ void __init plat_mem_setup(void)
crashk_end = crashk_base + crashk_size;
}
#endif
- /*
- * When allocating memory, we want incrementing addresses from
- * bootmem_alloc so the code in add_memory_region can merge
- * regions next to each other.
- */
cvmx_bootmem_lock();
while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
&& (total < max_memory)) {
+#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
__pa_symbol(&_end), -1,
0x100000,
CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#elif defined(CONFIG_HIGHMEM)
+ memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
+ 0x100000,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#else
+ memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
+ 0x100000,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#endif
if (memory >= 0) {
u64 size = mem_alloc_size;
@@ -942,7 +994,7 @@ void __init plat_mem_setup(void)
}
cvmx_bootmem_unlock();
#endif /* CONFIG_CRASH_DUMP */
-
+mem_alloc_done:
#ifdef CONFIG_CAVIUM_RESERVE32
/*
* Now that we've allocated the kernel memory it is safe to
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 10/11] MIPS: Add the concept of BOOT_MEM_KERNEL to boot_mem_map.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (8 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 09/11] MIPS: Octeon: Populate kernel memory from cvmx_bootmem named blocks Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 11/11] MIPS: Octeon: Add working hotplug CPU support Steven J. Hill
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, ralf, Carlos Munoz
From: David Daney <david.daney@cavium.com>
No change to memory initialization, but this gets us ready for the
next patches adding hotplug CPU and NUMA support for Octeon.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Carlos Munoz <cmunoz@caviumnetworks.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
---
arch/mips/include/asm/bootinfo.h | 1 +
arch/mips/kernel/setup.c | 30 +++++++++++++++++++++---------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index e26a093..71dd16e 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -90,6 +90,7 @@ extern unsigned long mips_machtype;
#define BOOT_MEM_ROM_DATA 2
#define BOOT_MEM_RESERVED 3
#define BOOT_MEM_INIT_RAM 4
+#define BOOT_MEM_KERNEL 5
/*
* A memory map that's built upon what was determined
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index fe39397..7a05882 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -189,9 +189,15 @@ static void __init print_memory_map(void)
const int field = 2 * sizeof(unsigned long);
for (i = 0; i < boot_mem_map.nr_map; i++) {
- printk(KERN_INFO " memory: %0*Lx @ %0*Lx ",
- field, (unsigned long long) boot_mem_map.map[i].size,
- field, (unsigned long long) boot_mem_map.map[i].addr);
+ if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) &&
+ (boot_mem_map.map[i].type == BOOT_MEM_KERNEL))
+ printk(KERN_INFO " memory: %.*s @ %.*s ",
+ field, "----------------",
+ field, "----------------");
+ else
+ printk(KERN_INFO " memory: %0*Lx @ %0*Lx ",
+ field, (unsigned long long) boot_mem_map.map[i].size,
+ field, (unsigned long long) boot_mem_map.map[i].addr);
switch (boot_mem_map.map[i].type) {
case BOOT_MEM_RAM:
@@ -200,6 +206,9 @@ static void __init print_memory_map(void)
case BOOT_MEM_INIT_RAM:
printk(KERN_CONT "(usable after init)\n");
break;
+ case BOOT_MEM_KERNEL:
+ printk(KERN_CONT "(kernel data and code)\n");
+ break;
case BOOT_MEM_ROM_DATA:
printk(KERN_CONT "(ROM data)\n");
break;
@@ -824,6 +833,7 @@ static void __init arch_mem_init(char **cmdline_p)
{
struct memblock_region *reg;
extern void plat_mem_setup(void);
+ phys_addr_t kernel_begin, init_begin, init_end, kernel_end;
/* call board setup routine */
plat_mem_setup();
@@ -834,12 +844,13 @@ static void __init arch_mem_init(char **cmdline_p)
* into another memory section you don't want that to be
* freed when the initdata is freed.
*/
- arch_mem_addpart(PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT,
- PFN_UP(__pa_symbol(&_edata)) << PAGE_SHIFT,
- BOOT_MEM_RAM);
- arch_mem_addpart(PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT,
- PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT,
- BOOT_MEM_INIT_RAM);
+ kernel_begin = PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT;
+ kernel_end = PFN_UP(__pa_symbol(&_end)) << PAGE_SHIFT;
+ init_begin = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
+ init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
+ arch_mem_addpart(kernel_begin, init_begin, BOOT_MEM_KERNEL);
+ arch_mem_addpart(init_end, kernel_end, BOOT_MEM_KERNEL);
+ arch_mem_addpart(init_begin, init_end, BOOT_MEM_INIT_RAM);
pr_info("Determined physical RAM map:\n");
print_memory_map();
@@ -949,6 +960,7 @@ static void __init resource_init(void)
case BOOT_MEM_RAM:
case BOOT_MEM_INIT_RAM:
case BOOT_MEM_ROM_DATA:
+ case BOOT_MEM_KERNEL:
res->name = "System RAM";
res->flags |= IORESOURCE_SYSRAM;
break;
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 11/11] MIPS: Octeon: Add working hotplug CPU support.
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
` (9 preceding siblings ...)
2017-11-14 4:30 ` [PATCH v3 10/11] MIPS: Add the concept of BOOT_MEM_KERNEL to boot_mem_map Steven J. Hill
@ 2017-11-14 4:30 ` Steven J. Hill
10 siblings, 0 replies; 24+ messages in thread
From: Steven J. Hill @ 2017-11-14 4:30 UTC (permalink / raw)
To: linux-mips
Cc: David Daney, ralf, Leonid Rosenboim, Chandrakala Chavva,
Carlos Munoz, Corey Minyard
From: David Daney <david.daney@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Carlos Munoz <cmunoz@caviumnetworks.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
---
arch/mips/Kconfig | 2 +-
arch/mips/cavium-octeon/octeon_boot.h | 95 ---------
arch/mips/cavium-octeon/setup.c | 2 +-
arch/mips/cavium-octeon/smp.c | 230 +++++++--------------
.../asm/mach-cavium-octeon/kernel-entry-init.h | 60 +++++-
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/include/asm/octeon/cvmx-coremask.h | 26 ++-
arch/mips/include/asm/octeon/cvmx.h | 15 +-
arch/mips/include/asm/octeon/octeon.h | 2 +
9 files changed, 179 insertions(+), 254 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/octeon_boot.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 475239d..6c85648 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -905,7 +905,7 @@ config CAVIUM_OCTEON_SOC
select EDAC_SUPPORT
select EDAC_ATOMIC_SCRUB
select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
+ select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_CAVIUM_OCTEON
select HW_HAS_PCI
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
deleted file mode 100644
index a6ce7c4..0000000
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2004, 2005 Cavium Networks
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __OCTEON_BOOT_H__
-#define __OCTEON_BOOT_H__
-
-#include <linux/types.h>
-
-struct boot_init_vector {
- /* First stage address - in ram instead of flash */
- uint64_t code_addr;
- /* Setup code for application, NOT application entry point */
- uint32_t app_start_func_addr;
- /* k0 is used for global data - needs to be passed to other cores */
- uint32_t k0_val;
- /* Address of boot info block structure */
- uint64_t boot_info_addr;
- uint32_t flags; /* flags */
- uint32_t pad;
-};
-
-/* similar to bootloader's linux_app_boot_info but without global data */
-struct linux_app_boot_info {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint32_t labi_signature;
- uint32_t start_core0_addr;
- uint32_t avail_coremask;
- uint32_t pci_console_active;
- uint32_t icache_prefetch_disable;
- uint32_t padding;
- uint64_t InitTLBStart_addr;
- uint32_t start_app_addr;
- uint32_t cur_exception_base;
- uint32_t no_mark_private_data;
- uint32_t compact_flash_common_base_addr;
- uint32_t compact_flash_attribute_base_addr;
- uint32_t led_display_base_addr;
-#else
- uint32_t start_core0_addr;
- uint32_t labi_signature;
-
- uint32_t pci_console_active;
- uint32_t avail_coremask;
-
- uint32_t padding;
- uint32_t icache_prefetch_disable;
-
- uint64_t InitTLBStart_addr;
-
- uint32_t cur_exception_base;
- uint32_t start_app_addr;
-
- uint32_t compact_flash_common_base_addr;
- uint32_t no_mark_private_data;
-
- uint32_t led_display_base_addr;
- uint32_t compact_flash_attribute_base_addr;
-#endif
-};
-
-/* If not to copy a lot of bootloader's structures
- here is only offset of requested member */
-#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c
-
-/* hardcoded in bootloader */
-#define LABI_ADDR_IN_BOOTLOADER 0x700
-
-#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
-
-#define LABI_SIGNATURE 0xAABBCC01
-
-/* from uboot-headers/octeon_mem_map.h */
-#define EXCEPTION_BASE_INCR (4 * 1024)
- /* Increment size for exception base addresses (4k minimum) */
-#define EXCEPTION_BASE_BASE 0
-#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800)
-#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE)
-
-#endif /* __OCTEON_BOOT_H__ */
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2855d8d..068787d 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -756,7 +756,7 @@ void __init prom_init(void)
if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
OCTEON_IS_MODEL(OCTEON_CN31XX))
cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
- else
+ else if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
/* Default to 64MB in the simulator to speed things up */
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index f08f175..8a3bfd3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -3,41 +3,41 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
+ * Copyright (C) 2004-2017 Cavium, Inc.
*/
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/sched/hotplug.h>
#include <linux/sched/task_stack.h>
#include <linux/init.h>
#include <linux/export.h>
-#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/cvmx-boot-vector.h>
-#include "octeon_boot.h"
-
-volatile unsigned long octeon_processor_boot = 0xff;
-volatile unsigned long octeon_processor_sp;
-volatile unsigned long octeon_processor_gp;
+unsigned long octeon_processor_boot = 0xff;
+unsigned long octeon_processor_sp;
+unsigned long octeon_processor_gp;
#ifdef CONFIG_RELOCATABLE
-volatile unsigned long octeon_processor_relocated_kernel_entry;
+unsigned long octeon_processor_relocated_kernel_entry;
#endif /* CONFIG_RELOCATABLE */
#ifdef CONFIG_HOTPLUG_CPU
-uint64_t octeon_bootloader_entry_addr;
-EXPORT_SYMBOL(octeon_bootloader_entry_addr);
+static struct cvmx_boot_vector_element *octeon_bootvector;
+static void *octeon_hotplug_entry_raw;
#endif
-extern void kernel_entry(unsigned long arg1, ...);
+/* State of each CPU. */
+DEFINE_PER_CPU(int, cpu_state);
static void octeon_icache_flush(void)
{
@@ -99,57 +99,32 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
void octeon_send_ipi_single(int cpu, unsigned int action)
{
int coreid = cpu_logical_map(cpu);
- /*
- pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
- coreid, action);
- */
+
cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}
static inline void octeon_send_ipi_mask(const struct cpumask *mask,
unsigned int action)
{
- unsigned int i;
-
- for_each_cpu(i, mask)
- octeon_send_ipi_single(i, action);
-}
-
-/**
- * Detect available CPUs, populate cpu_possible_mask
- */
-static void octeon_smp_hotplug_setup(void)
-{
-#ifdef CONFIG_HOTPLUG_CPU
- struct linux_app_boot_info *labi;
-
- if (!setup_max_cpus)
- return;
-
- labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
- if (labi->labi_signature != LABI_SIGNATURE) {
- pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
- return;
- }
+ int cpu;
- octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
-#endif
+ for_each_cpu(cpu, mask)
+ octeon_send_ipi_single(cpu, action);
}
-static void __init octeon_smp_setup(void)
+static void octeon_smp_setup(void)
{
const int coreid = cvmx_get_core_num();
int cpus;
int id;
- struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
-
#ifdef CONFIG_HOTPLUG_CPU
- int core_mask = octeon_get_boot_coremask();
unsigned int num_cores = cvmx_octeon_num_cores();
+ unsigned long t;
#endif
+ struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
/* The present CPUs are initially just the boot cpu (CPU 0). */
- for (id = 0; id < NR_CPUS; id++) {
+ for (id = 0; id < num_possible_cpus(); id++) {
set_cpu_possible(id, id == 0);
set_cpu_present(id, id == 0);
}
@@ -159,8 +134,9 @@ static void __init octeon_smp_setup(void)
/* The present CPUs get the lowest CPU numbers. */
cpus = 1;
- for (id = 0; id < NR_CPUS; id++) {
- if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
+ for (id = 0; id < CONFIG_MIPS_NR_CPU_NR_MAP; id++) {
+ if ((id != coreid) &&
+ cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
set_cpu_possible(cpus, true);
set_cpu_present(cpus, true);
__cpu_number_map[id] = cpus;
@@ -170,14 +146,21 @@ static void __init octeon_smp_setup(void)
}
#ifdef CONFIG_HOTPLUG_CPU
+ octeon_bootvector = cvmx_boot_vector_get();
+ if (!octeon_bootvector) {
+ pr_err("Error: Cannot allocate boot vector.\n");
+ return;
+ }
+ t = __pa_symbol(octeon_hotplug_entry);
+ octeon_hotplug_entry_raw = phys_to_virt(t);
+
/*
* The possible CPUs are all those present on the chip. We
* will assign CPU numbers for possible cores as well. Cores
* are always consecutively numberd from 0.
*/
- for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
- id < num_cores && id < NR_CPUS; id++) {
- if (!(core_mask & (1 << id))) {
+ for (id = 0; id < num_cores && id < num_possible_cpus(); id++) {
+ if (!(cvmx_coremask_is_core_set(&sysinfo->core_mask, id))) {
set_cpu_possible(cpus, true);
__cpu_number_map[id] = cpus;
__cpu_logical_map[cpus] = id;
@@ -185,8 +168,6 @@ static void __init octeon_smp_setup(void)
}
}
#endif
-
- octeon_smp_hotplug_setup();
}
@@ -209,13 +190,33 @@ int plat_post_relocation(long offset)
static int octeon_boot_secondary(int cpu, struct task_struct *idle)
{
int count;
+ int node;
+ int coreid = cpu_logical_map(cpu);
+ per_cpu(cpu_state, smp_processor_id()) = CPU_UP_PREPARE;
+#ifdef CONFIG_HOTPLUG_CPU
+ octeon_bootvector[coreid].target_ptr = (uint64_t)octeon_hotplug_entry_raw;
+#endif
+ mb();
+ /* Convert coreid to node,core spair and send NMI to target core */
+ node = cvmx_coremask_core_to_node(coreid);
+ coreid = cvmx_coremask_core_on_node(coreid);
+ if (octeon_has_feature(OCTEON_FEATURE_CIU3))
+ cvmx_write_csr_node(node, CVMX_CIU3_NMI, (1ull << coreid));
+ else
+ cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid));
pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
cpu_logical_map(cpu));
octeon_processor_sp = __KSTK_TOS(idle);
octeon_processor_gp = (unsigned long)(task_thread_info(idle));
- octeon_processor_boot = cpu_logical_map(cpu);
+ /* This barrier is needed to guarantee the following is done last */
+ mb();
+
+ /* Indicate which core is being brought up out of pan */
+ octeon_processor_boot = coreid;
+
+ /* Push the last update out before polling */
mb();
count = 10000;
@@ -223,12 +224,16 @@ static int octeon_boot_secondary(int cpu, struct task_struct *idle)
/* Waiting for processor to get the SP and GP */
udelay(1);
count--;
+ mb();
}
if (count == 0) {
pr_err("Secondary boot timeout\n");
return -ETIMEDOUT;
}
+ octeon_processor_boot = ~0ul;
+ mb();
+
return 0;
}
@@ -256,11 +261,24 @@ static void octeon_init_secondary(void)
*/
static void __init octeon_prepare_cpus(unsigned int max_cpus)
{
+ u64 mask;
+ u64 coreid;
+
/*
* Only the low order mailbox bits are used for IPIs, leave
* the other bits alone.
*/
- cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ mask = 0xff;
+ else
+ mask = 0xffff;
+
+ coreid = cvmx_get_core_num();
+
+ /* Clear pending mailbox interrupts */
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), mask);
+
+ /* Attach mailbox interrupt handler */
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
mailbox_interrupt)) {
@@ -275,6 +293,8 @@ static void __init octeon_prepare_cpus(unsigned int max_cpus)
static void octeon_smp_finish(void)
{
octeon_user_io_init();
+ per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
+ mb();
/* to generate the first CPU timer interrupt */
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
@@ -283,9 +303,6 @@ static void octeon_smp_finish(void)
#ifdef CONFIG_HOTPLUG_CPU
-/* State of each CPU. */
-DEFINE_PER_CPU(int, cpu_state);
-
static int octeon_cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
@@ -293,9 +310,6 @@ static int octeon_cpu_disable(void)
if (cpu == 0)
return -EBUSY;
- if (!octeon_bootloader_entry_addr)
- return -ENOTSUPP;
-
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
octeon_fixup_irqs();
@@ -308,40 +322,8 @@ static int octeon_cpu_disable(void)
static void octeon_cpu_die(unsigned int cpu)
{
- int coreid = cpu_logical_map(cpu);
- uint32_t mask, new_mask;
- const struct cvmx_bootmem_named_block_desc *block_desc;
-
while (per_cpu(cpu_state, cpu) != CPU_DEAD)
cpu_relax();
-
- /*
- * This is a bit complicated strategics of getting/settig available
- * cores mask, copied from bootloader
- */
-
- mask = 1 << coreid;
- /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
- block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
-
- if (!block_desc) {
- struct linux_app_boot_info *labi;
-
- labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
-
- labi->avail_coremask |= mask;
- new_mask = labi->avail_coremask;
- } else { /* alternative, already initialized */
- uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
- AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
- *p |= mask;
- new_mask = *p;
- }
-
- pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
- mb();
- cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
- cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}
void play_dead(void)
@@ -349,71 +331,17 @@ void play_dead(void)
int cpu = cpu_number_map(cvmx_get_core_num());
idle_task_exit();
- octeon_processor_boot = 0xff;
per_cpu(cpu_state, cpu) = CPU_DEAD;
+ local_irq_disable();
- mb();
-
- while (1) /* core will be reset here */
- ;
-}
-
-static void start_after_reset(void)
-{
- kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
-}
-
-static int octeon_update_boot_vector(unsigned int cpu)
-{
-
- int coreid = cpu_logical_map(cpu);
- uint32_t avail_coremask;
- const struct cvmx_bootmem_named_block_desc *block_desc;
- struct boot_init_vector *boot_vect =
- (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
-
- block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
-
- if (!block_desc) {
- struct linux_app_boot_info *labi;
-
- labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
-
- avail_coremask = labi->avail_coremask;
- labi->avail_coremask &= ~(1 << coreid);
- } else { /* alternative, already initialized */
- avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
- block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
- }
-
- if (!(avail_coremask & (1 << coreid))) {
- /* core not available, assume, that caught by simple-executive */
- cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
- cvmx_write_csr(CVMX_CIU_PP_RST, 0);
- }
-
- boot_vect[coreid].app_start_func_addr =
- (uint32_t) (unsigned long) start_after_reset;
- boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
-
- mb();
-
- cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
-
- return 0;
-}
-
-static int register_cavium_notifier(void)
-{
- return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
- "mips/cavium:prepare",
- octeon_update_boot_vector, NULL);
+ /* core will be reset here */
+ while (1)
+ asm volatile (" wait\n");
}
-late_initcall(register_cavium_notifier);
#endif /* CONFIG_HOTPLUG_CPU */
-const struct plat_smp_ops octeon_smp_ops = {
+static struct plat_smp_ops octeon_smp_ops = {
.send_ipi_single = octeon_send_ipi_single,
.send_ipi_mask = octeon_send_ipi_mask,
.init_secondary = octeon_init_secondary,
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38c..bef5092 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -3,11 +3,13 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2005-2008 Cavium Networks, Inc
+ * Copyright (C) 2005-2017 Cavium, Inc
*/
#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+#include <asm/octeon/cvmx-asm.h>
+
#define CP0_CVMCTL_REG $9, 7
#define CP0_CVMMEMCTL_REG $11,7
#define CP0_PRID_REG $15, 0
@@ -26,6 +28,62 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+#ifdef CONFIG_HOTPLUG_CPU
+ b 7f
+FEXPORT(octeon_hotplug_entry)
+ move a0, zero
+ move a1, zero
+ move a2, zero
+ move a3, zero
+7:
+#endif /* CONFIG_HOTPLUG_CPU */
+ mfc0 v0, CP0_STATUS
+ /* Force 64-bit addressing enabled */
+ ori v0, v0, (ST0_UX | ST0_SX | ST0_KX)
+ /* Clear NMI and SR as they are sometimes restored and 0 -> 1
+ * transitions are not allowed
+ */
+ li v1, ~(ST0_NMI | ST0_SR)
+ and v0, v1
+ mtc0 v0, CP0_STATUS
+
+ # Clear the TLB.
+ mfc0 v0, CP0_CONFIG, 1
+ ext v0, v0, MIPS_CONF1_TLBS_SHIFT, MIPS_CONF1_TLBS_SIZE
+ mfc0 v1, CP0_CONFIG, 3
+ bgez v1, 1f
+ mfc0 v1, CP0_CONFIG, 4
+ andi v1, v1, MIPS_CONF4_MMUSIZEEXT_SIZE
+ ins v0, v1, MIPS_CONF1_TLBS_SIZE, MIPS_CONF4_MMUSIZEEXT_SIZE
+1: # Number of TLBs in v0
+
+ dmtc0 zero, $2, 0 # EntryLo0
+ dmtc0 zero, $3, 0 # EntryLo1
+ dmtc0 zero, $5, 0 # PageMask
+ dla t0, 0xffffffff90000000
+10:
+ dmtc0 t0, $10, 0 # EntryHi
+ tlbp
+ mfc0 t1, $0, 0 # Index
+ bltz t1, 1f
+ tlbr
+ dmtc0 zero, $2, 0 # EntryLo0
+ dmtc0 zero, $3, 0 # EntryLo1
+ dmtc0 zero, $5, 0 # PageMask
+ tlbwi # Make it a 'normal' sized page
+ daddiu t0, t0, 8192
+ b 10b
+1:
+ mtc0 v0, $0, 0 # Index
+ tlbwi
+ .set noreorder
+ bne v0, zero, 10b
+ addiu v0, v0, -1
+ .set reorder
+
+ mtc0 zero, $0, 0 # Index
+ dmtc0 zero, $10, 0 # EntryHi
+
# Read the cavium mem control register
dmfc0 v0, CP0_CVMMEMCTL_REG
# Clear the lower 6 bits, the CVMSEG size
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a681092..3fa2352 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -633,6 +633,7 @@
#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
+#define MIPS_CONF4_MMUSIZEEXT_SIZE (8)
#define MIPS_CONF4_FTLBSETS_SHIFT (0)
#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
diff --git a/arch/mips/include/asm/octeon/cvmx-coremask.h b/arch/mips/include/asm/octeon/cvmx-coremask.h
index 097dc09..625cf94 100644
--- a/arch/mips/include/asm/octeon/cvmx-coremask.h
+++ b/arch/mips/include/asm/octeon/cvmx-coremask.h
@@ -29,7 +29,6 @@
#ifndef __CVMX_COREMASK_H__
#define __CVMX_COREMASK_H__
-#define CVMX_MIPS_MAX_CORES 1024
/* bits per holder */
#define CVMX_COREMASK_ELTSZ 64
@@ -86,4 +85,29 @@ static inline void cvmx_coremask_clear_core(struct cvmx_coremask *pcm, int core)
pcm->coremask_bitmap[i] &= ~(1ull << n);
}
+/**
+ * For multi-node systems, return the node a core belongs to.
+ *
+ * @param core - core number (0-1023)
+ *
+ * @return node number core belongs to
+ */
+static inline int cvmx_coremask_core_to_node(int core)
+{
+ return (core >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
+}
+
+/**
+ * Given a core number on a multi-node system, return the core number for a
+ * particular node.
+ *
+ * @param core - global core number
+ *
+ * @returns core number local to the node.
+ */
+static inline int cvmx_coremask_core_on_node(int core)
+{
+ return (core & GENMASK((CVMX_NODE_NO_SHIFT - 1), 0));
+}
+
#endif /* __CVMX_COREMASK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 392556a..6d9851a 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -53,6 +53,17 @@ enum cvmx_mips_space {
#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
#endif
+#define CVMX_MAX_CORES (48)
+#define CVMX_MIPS_MAX_CORE_BITS (10) /** Maximum # of bits to define cores */
+#define CVMX_MIPS_MAX_CORES (1 << CVMX_MIPS_MAX_CORE_BITS)
+#define CVMX_NODE_NO_SHIFT (7) /* Maximum # of bits to define core in node */
+#define CVMX_NODE_BITS (2) /* Number of bits to define a node */
+#define CVMX_NODE_MASK (CVMX_MAX_NODES - 1)
+#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
+#define CVMX_NODE_IO_SHIFT (36)
+#define CVMX_NODE_MEM_SHIFT (40)
+#define CVMX_NODE_IO_MASK ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
+
#include <asm/octeon/cvmx-asm.h>
#include <asm/octeon/octeon-model.h>
@@ -83,7 +94,6 @@ enum cvmx_mips_space {
#define cvmx_dprintf(...) {}
#endif
-#define CVMX_MAX_CORES (16)
#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
@@ -339,9 +349,6 @@ static inline unsigned int cvmx_get_core_num(void)
return core_num;
}
-/* Maximum # of bits to define core in node */
-#define CVMX_NODE_NO_SHIFT 7
-#define CVMX_NODE_MASK 0x3
static inline unsigned int cvmx_get_node_num(void)
{
unsigned int core_num = cvmx_get_core_num();
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6..0980628 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -355,6 +355,8 @@ extern uint64_t octeon_bootloader_entry_addr;
extern void (*octeon_irq_setup_secondary)(void);
+extern asmlinkage void octeon_hotplug_entry(void);
+
typedef void (*octeon_irq_ip4_handler_t)(void);
void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
--
2.1.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks.
2017-11-14 4:30 ` [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks Steven J. Hill
@ 2017-11-14 15:39 ` Ralf Baechle
2017-11-14 15:43 ` Ralf Baechle
2017-11-14 17:57 ` David Daney
0 siblings, 2 replies; 24+ messages in thread
From: Ralf Baechle @ 2017-11-14 15:39 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips, Chad Reese, David Daney
On Mon, Nov 13, 2017 at 10:30:17PM -0600, Steven J. Hill wrote:
> From: Chad Reese <kreese@caviumnetworks.com>
>
> Flushing the writes lets other CPUs waiting for the lock to get it
> sooner.
>
> Signed-off-by: Chad Reese <kreese@caviumnetworks.com>
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> ---
> arch/mips/include/asm/bitops.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
> index fa57cef..da1b871 100644
> --- a/arch/mips/include/asm/bitops.h
> +++ b/arch/mips/include/asm/bitops.h
> @@ -456,6 +456,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
> {
> smp_mb__before_llsc();
> __clear_bit(nr, addr);
> + nudge_writes();
> }
Hmm...
This patch looks ok, it's more the definition of nudge_writes() which I'm
concerned about. __clear_bit_unlock() does not need a memory barrier
after __clear_bit() but for non-Octeon processors nudge_writes() expands
into one anyway.
The good news is nudge_writes() is currently unused anyway so we can
change the definition to something like nudge_writes do { } while (0)
for the Octeon. Suggested patch below.
The Octeon definition of nudge_writes() has a memory clobber and I'm
wondering if that one is actually required or if we could make things a
little easier on the compiler by removing it.
Ralf
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/barrier.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index a5eb1bb199a7..0e8e6afbf80a 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -216,7 +216,7 @@
#else
#define smp_mb__before_llsc() smp_llsc_mb()
#define __smp_mb__before_llsc() smp_llsc_mb()
-#define nudge_writes() mb()
+#define nudge_writes() do { } while (0)
#endif
#define __smp_mb__before_atomic() __smp_mb__before_llsc()
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn'
2017-11-14 4:30 ` [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn' Steven J. Hill
@ 2017-11-14 15:40 ` Ralf Baechle
0 siblings, 0 replies; 24+ messages in thread
From: Ralf Baechle @ 2017-11-14 15:40 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips
On Mon, Nov 13, 2017 at 10:30:18PM -0600, Steven J. Hill wrote:
> Date: Mon, 13 Nov 2017 22:30:18 -0600
> From: "Steven J. Hill" <steven.hill@cavium.com>
> To: linux-mips@linux-mips.org
> Cc: "Steven J. Hill" <Steven.Hill@cavium.com>, ralf@linux-mips.org
> Subject: [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn'
> Content-Type: text/plain
>
> From: "Steven J. Hill" <Steven.Hill@cavium.com>
>
> 'lastpfn' is never used for anything. Remove it.
>
> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> Acked-by: David Daney <david.daney@cavium.com
> ---
> arch/mips/mm/init.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
> index 5f6ea7d..84b7b59 100644
> --- a/arch/mips/mm/init.c
> +++ b/arch/mips/mm/init.c
> @@ -402,7 +402,6 @@ int page_is_ram(unsigned long pagenr)
> void __init paging_init(void)
> {
> unsigned long max_zone_pfns[MAX_NR_ZONES];
> - unsigned long lastpfn __maybe_unused;
>
> pagetable_init();
>
> @@ -416,17 +415,14 @@ void __init paging_init(void)
> max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
> #endif
> max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
> - lastpfn = max_low_pfn;
> #ifdef CONFIG_HIGHMEM
> max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
> - lastpfn = highend_pfn;
>
> if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
> printk(KERN_WARNING "This processor doesn't support highmem."
> " %ldk highmem ignored\n",
> (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
> max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
> - lastpfn = max_low_pfn;
> }
> #endif
This cleanup is an excellent demonstration for why __maybe_unused is a
less than great idea.
Ralf
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks.
2017-11-14 15:39 ` Ralf Baechle
@ 2017-11-14 15:43 ` Ralf Baechle
2017-11-14 17:57 ` David Daney
1 sibling, 0 replies; 24+ messages in thread
From: Ralf Baechle @ 2017-11-14 15:43 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips, Chad Reese, David Daney
On Tue, Nov 14, 2017 at 04:39:58PM +0100, Ralf Baechle wrote:
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>
> arch/mips/include/asm/barrier.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
> index a5eb1bb199a7..0e8e6afbf80a 100644
> --- a/arch/mips/include/asm/barrier.h
> +++ b/arch/mips/include/asm/barrier.h
> @@ -216,7 +216,7 @@
> #else
> #define smp_mb__before_llsc() smp_llsc_mb()
> #define __smp_mb__before_llsc() smp_llsc_mb()
> -#define nudge_writes() mb()
> +#define nudge_writes() do { } while (0)
> #endif
>
> #define __smp_mb__before_atomic() __smp_mb__before_llsc()
And patchwork once again failed to recognice this as a new patch and
filed it as a reply to a previous patch.
Which is not so bad if it's my patch but it may easily cause others'
submissions to be missed.
Ralf
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks.
2017-11-14 15:39 ` Ralf Baechle
2017-11-14 15:43 ` Ralf Baechle
@ 2017-11-14 17:57 ` David Daney
1 sibling, 0 replies; 24+ messages in thread
From: David Daney @ 2017-11-14 17:57 UTC (permalink / raw)
To: Ralf Baechle, Steven J. Hill; +Cc: linux-mips, Chad Reese, David Daney
On 11/14/2017 07:39 AM, Ralf Baechle wrote:
> On Mon, Nov 13, 2017 at 10:30:17PM -0600, Steven J. Hill wrote:
>
>> From: Chad Reese <kreese@caviumnetworks.com>
>>
>> Flushing the writes lets other CPUs waiting for the lock to get it
>> sooner.
>>
>> Signed-off-by: Chad Reese <kreese@caviumnetworks.com>
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
>> ---
>> arch/mips/include/asm/bitops.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
>> index fa57cef..da1b871 100644
>> --- a/arch/mips/include/asm/bitops.h
>> +++ b/arch/mips/include/asm/bitops.h
>> @@ -456,6 +456,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
>> {
>> smp_mb__before_llsc();
>> __clear_bit(nr, addr);
>> + nudge_writes();
>> }
>
> Hmm...
>
> This patch looks ok, it's more the definition of nudge_writes() which I'm
> concerned about. __clear_bit_unlock() does not need a memory barrier
> after __clear_bit() but for non-Octeon processors nudge_writes() expands
> into one anyway.
>
> The good news is nudge_writes() is currently unused anyway so we can
> change the definition to something like nudge_writes do { } while (0)
> for the Octeon. Suggested patch below.
>
> The Octeon definition of nudge_writes() has a memory clobber and I'm
> wondering if that one is actually required or if we could make things a
> little easier on the compiler by removing it.
The nudging operation (SYNCW) in OCTEON only needs to be ordered after
the store it is nudging out. I am not sure if "asm volatile" is enough
to do the ordering.
>
> Ralf
>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>
> arch/mips/include/asm/barrier.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
> index a5eb1bb199a7..0e8e6afbf80a 100644
> --- a/arch/mips/include/asm/barrier.h
> +++ b/arch/mips/include/asm/barrier.h
> @@ -216,7 +216,7 @@
> #else
> #define smp_mb__before_llsc() smp_llsc_mb()
> #define __smp_mb__before_llsc() smp_llsc_mb()
> -#define nudge_writes() mb()
> +#define nudge_writes() do { } while (0)
> #endif
>
> #define __smp_mb__before_atomic() __smp_mb__before_llsc()
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 4:30 ` [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere Steven J. Hill
@ 2017-11-14 19:08 ` Ralf Baechle
2017-11-14 20:30 ` James Hogan
2017-11-27 18:56 ` David Daney
1 sibling, 1 reply; 24+ messages in thread
From: Ralf Baechle @ 2017-11-14 19:08 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips
On Mon, Nov 13, 2017 at 10:30:20PM -0600, Steven J. Hill wrote:
> From: "Steven J. Hill" <Steven.Hill@cavium.com>
>
> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> Acked-by: David Daney <david.daney@cavium.com>
> ---
> arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
> arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
> arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
> arch/mips/pci/pcie-octeon.c | 12 ++++++------
> 5 files changed, 17 insertions(+), 26 deletions(-)
>
> diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
> index f24be0b..75108ec 100644
> --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
> +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
> @@ -862,7 +862,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
> */
> cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
>
> - cvmx_wait(100000000ull);
> + __delay(100000000ull);
>
> for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
> retry_cnt = 100000;
> diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
> index 459e3b1..f51957a 100644
> --- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
> +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
> @@ -215,7 +215,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
> spxx_clk_ctl.u64 = 0;
> spxx_clk_ctl.s.runbist = 1;
> cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
> - cvmx_wait(10 * MS);
> + __delay(10 * MS);
At this place and many others cvmx_wait() was used to wait for a number
of miliseconds, so I think it should better be replaced with something
like mdelay(10).
> spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
> if (spxx_bist_stat.s.stat0)
> cvmx_dprintf
> @@ -265,14 +265,14 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
> spxx_clk_ctl.s.rcvtrn = 0;
> spxx_clk_ctl.s.srxdlck = 0;
> cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
> - cvmx_wait(100 * MS);
> + __delay(100 * MS);
mdelay(100);
> /* Reset SRX0 DLL */
> spxx_clk_ctl.s.srxdlck = 1;
> cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
>
> /* Waiting for Inf0 Spi4 RX DLL to lock */
> - cvmx_wait(100 * MS);
mdelay(100);
After these three substitions I think the variable MS in cvmx_spi_reset_cb()
will be unused.
Or will __delay() be used before bogomips is calibrated?
> /* Enable dynamic alignment */
> spxx_trn4_ctl.s.trntest = 0;
> @@ -527,7 +527,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
> spxx_clk_ctl.s.rcvtrn = 1;
> spxx_clk_ctl.s.srxdlck = 1;
> cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
> - cvmx_wait(1000 * MS);
mdelay(1000);
>
> /* SRX0 clear the boot bit */
> spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
> @@ -536,7 +536,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
>
> /* Wait for the training sequence to complete */
> cvmx_dprintf("SPI%d: Waiting for training\n", interface);
> - cvmx_wait(1000 * MS);
> + __delay(1000 * MS);
mdelay(1000);
> /* Wait a really long time here */
> timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
> /*
> diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
> index c00501d..29ae636 100644
> --- a/arch/mips/include/asm/octeon/cvmx-fpa.h
> +++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
> @@ -36,6 +36,8 @@
> #ifndef __CVMX_FPA_H__
> #define __CVMX_FPA_H__
>
> +#include <linux/delay.h>
> +
> #include <asm/octeon/cvmx-address.h>
> #include <asm/octeon/cvmx-fpa-defs.h>
>
> @@ -165,7 +167,7 @@ static inline void cvmx_fpa_enable(void)
> }
>
> /* Enforce a 10 cycle delay between config and enable */
> - cvmx_wait(10);
> + __delay(10);
> }
>
> /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
> diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
> index 205ab2c..25854ab 100644
> --- a/arch/mips/include/asm/octeon/cvmx.h
> +++ b/arch/mips/include/asm/octeon/cvmx.h
> @@ -30,6 +30,7 @@
>
> #include <linux/kernel.h>
> #include <linux/string.h>
> +#include <linux/delay.h>
>
> enum cvmx_mips_space {
> CVMX_MIPS_SPACE_XKSEG = 3LL,
> @@ -429,18 +430,6 @@ static inline uint64_t cvmx_get_cycle(void)
> }
>
> /**
> - * Wait for the specified number of cycle
> - *
> - */
> -static inline void cvmx_wait(uint64_t cycles)
> -{
> - uint64_t done = cvmx_get_cycle() + cycles;
> -
> - while (cvmx_get_cycle() < done)
> - ; /* Spin */
> -}
> -
> -/**
> * Reads a chip global cycle counter. This counts CPU cycles since
> * chip reset. The counter is 64 bit.
> * This register does not exist on CN38XX pass 1 silicion
> @@ -481,7 +470,7 @@ static inline uint64_t cvmx_get_cycle_global(void)
> result = -1; \
> break; \
> } else \
> - cvmx_wait(100); \
> + __delay(100); \
> } \
> } while (0); \
> result; \
> diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
> index fd28874..87ba86b 100644
> --- a/arch/mips/pci/pcie-octeon.c
> +++ b/arch/mips/pci/pcie-octeon.c
> @@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
> cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
> return -1;
> }
> - cvmx_wait(10000);
> + __delay(10000);
> pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
> } while (pciercx_cfg032.s.dlla == 0);
>
> @@ -821,7 +821,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
> * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
> * fixed number of cycles.
> */
> - cvmx_wait(400000);
> + __delay(400000);
>
> /*
> * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
> @@ -1018,7 +1018,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
> i = in_p_offset;
> while (i--) {
> cvmx_write64_uint32(write_address, 0);
> - cvmx_wait(10000);
> + __delay(10000);
> }
>
> /*
> @@ -1034,7 +1034,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
> dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
> old_in_fif_p_count = dbg_data.s.data & 0xff;
> cvmx_write64_uint32(write_address, 0);
> - cvmx_wait(10000);
> + __delay(10000);
> dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
> in_fif_p_count = dbg_data.s.data & 0xff;
> } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
> @@ -1053,7 +1053,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
> cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
> while (in_fif_p_count != 0) {
> cvmx_write64_uint32(write_address, 0);
> - cvmx_wait(10000);
> + __delay(10000);
> in_fif_p_count = (in_fif_p_count + 1) & 0xff;
> }
> /*
> @@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
> do {
> if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
> return -1;
> - cvmx_wait(10000);
> + __delay(10000);
> pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
> } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
Ralf
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 19:08 ` Ralf Baechle
@ 2017-11-14 20:30 ` James Hogan
2017-11-14 20:30 ` James Hogan
2017-11-14 20:45 ` Ralf Baechle
0 siblings, 2 replies; 24+ messages in thread
From: James Hogan @ 2017-11-14 20:30 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Steven J. Hill, linux-mips
[-- Attachment #1: Type: text/plain, Size: 609 bytes --]
On Tue, Nov 14, 2017 at 08:08:28PM +0100, Ralf Baechle wrote:
> On Mon, Nov 13, 2017 at 10:30:20PM -0600, Steven J. Hill wrote:
> > From: "Steven J. Hill" <Steven.Hill@cavium.com>
>
> At this place and many others cvmx_wait() was used to wait for a number
> of miliseconds, so I think it should better be replaced with something
> like mdelay(10).
Note that this patch, along with the nudges one and the lastpfn one, is
already queued for 4.15:
git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
branch: mips-next
so any fixes to it will have to be made on top.
Cheers
James
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 20:30 ` James Hogan
@ 2017-11-14 20:30 ` James Hogan
2017-11-14 20:45 ` Ralf Baechle
1 sibling, 0 replies; 24+ messages in thread
From: James Hogan @ 2017-11-14 20:30 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Steven J. Hill, linux-mips
[-- Attachment #1: Type: text/plain, Size: 609 bytes --]
On Tue, Nov 14, 2017 at 08:08:28PM +0100, Ralf Baechle wrote:
> On Mon, Nov 13, 2017 at 10:30:20PM -0600, Steven J. Hill wrote:
> > From: "Steven J. Hill" <Steven.Hill@cavium.com>
>
> At this place and many others cvmx_wait() was used to wait for a number
> of miliseconds, so I think it should better be replaced with something
> like mdelay(10).
Note that this patch, along with the nudges one and the lastpfn one, is
already queued for 4.15:
git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
branch: mips-next
so any fixes to it will have to be made on top.
Cheers
James
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 20:30 ` James Hogan
2017-11-14 20:30 ` James Hogan
@ 2017-11-14 20:45 ` Ralf Baechle
1 sibling, 0 replies; 24+ messages in thread
From: Ralf Baechle @ 2017-11-14 20:45 UTC (permalink / raw)
To: James Hogan; +Cc: Steven J. Hill, linux-mips
On Tue, Nov 14, 2017 at 08:30:47PM +0000, James Hogan wrote:
> On Tue, Nov 14, 2017 at 08:08:28PM +0100, Ralf Baechle wrote:
> > On Mon, Nov 13, 2017 at 10:30:20PM -0600, Steven J. Hill wrote:
> > > From: "Steven J. Hill" <Steven.Hill@cavium.com>
> >
> > At this place and many others cvmx_wait() was used to wait for a number
> > of miliseconds, so I think it should better be replaced with something
> > like mdelay(10).
>
> Note that this patch, along with the nudges one and the lastpfn one, is
> already queued for 4.15:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
> branch: mips-next
>
> so any fixes to it will have to be made on top.
Fair enough, leave 'em in.
Ralf
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-14 4:30 ` [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere Steven J. Hill
2017-11-14 19:08 ` Ralf Baechle
@ 2017-11-27 18:56 ` David Daney
2017-11-28 11:04 ` James Hogan
1 sibling, 1 reply; 24+ messages in thread
From: David Daney @ 2017-11-27 18:56 UTC (permalink / raw)
To: Steven J. Hill, linux-mips; +Cc: ralf
On 11/13/2017 08:30 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <Steven.Hill@cavium.com>
>
> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> Acked-by: David Daney <david.daney@cavium.com>
> ---
> arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
> arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
> arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
> arch/mips/pci/pcie-octeon.c | 12 ++++++------
> 5 files changed, 17 insertions(+), 26 deletions(-)
>
WTF:
drivers/staging/octeon-usb/octeon-hcd.c: In function 'cvmx_fifo_setup':
drivers/staging/octeon-usb/octeon-hcd.c:636:2: error: implicit
declaration of function 'cvmx_wait' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
Why was this patch submitted and merged without running git-grep on
cvmx_wait?
Steven, send a patch to fix the breakage.
David.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-27 18:56 ` David Daney
@ 2017-11-28 11:04 ` James Hogan
2017-11-28 11:04 ` James Hogan
2017-11-28 18:44 ` David Daney
0 siblings, 2 replies; 24+ messages in thread
From: James Hogan @ 2017-11-28 11:04 UTC (permalink / raw)
To: David Daney; +Cc: Steven J. Hill, linux-mips, ralf
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Hi David,
On Mon, Nov 27, 2017 at 10:56:33AM -0800, David Daney wrote:
> On 11/13/2017 08:30 PM, Steven J. Hill wrote:
> > From: "Steven J. Hill" <Steven.Hill@cavium.com>
> >
> > Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> > Acked-by: David Daney <david.daney@cavium.com>
> > ---
> > arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
> > arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
> > arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
> > arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
> > arch/mips/pci/pcie-octeon.c | 12 ++++++------
> > 5 files changed, 17 insertions(+), 26 deletions(-)
> >
>
> WTF:
>
> drivers/staging/octeon-usb/octeon-hcd.c: In function 'cvmx_fifo_setup':
> drivers/staging/octeon-usb/octeon-hcd.c:636:2: error: implicit
> declaration of function 'cvmx_wait' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
>
> Why was this patch submitted and merged without running git-grep on
> cvmx_wait?
I guess I put too much store by your ack ;-)
Lesson learned, I'll grep next time.
>
> Steven, send a patch to fix the breakage.
See this patch & thread which you were Cc'd on:
https://lkml.kernel.org/r/20171117075010.24131-1-aaro.koskinen@iki.fi
Cheers
James
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-28 11:04 ` James Hogan
@ 2017-11-28 11:04 ` James Hogan
2017-11-28 18:44 ` David Daney
1 sibling, 0 replies; 24+ messages in thread
From: James Hogan @ 2017-11-28 11:04 UTC (permalink / raw)
To: David Daney; +Cc: Steven J. Hill, linux-mips, ralf
[-- Attachment #1: Type: text/plain, Size: 1367 bytes --]
Hi David,
On Mon, Nov 27, 2017 at 10:56:33AM -0800, David Daney wrote:
> On 11/13/2017 08:30 PM, Steven J. Hill wrote:
> > From: "Steven J. Hill" <Steven.Hill@cavium.com>
> >
> > Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
> > Acked-by: David Daney <david.daney@cavium.com>
> > ---
> > arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
> > arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
> > arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
> > arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
> > arch/mips/pci/pcie-octeon.c | 12 ++++++------
> > 5 files changed, 17 insertions(+), 26 deletions(-)
> >
>
> WTF:
>
> drivers/staging/octeon-usb/octeon-hcd.c: In function 'cvmx_fifo_setup':
> drivers/staging/octeon-usb/octeon-hcd.c:636:2: error: implicit
> declaration of function 'cvmx_wait' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
>
> Why was this patch submitted and merged without running git-grep on
> cvmx_wait?
I guess I put too much store by your ack ;-)
Lesson learned, I'll grep next time.
>
> Steven, send a patch to fix the breakage.
See this patch & thread which you were Cc'd on:
https://lkml.kernel.org/r/20171117075010.24131-1-aaro.koskinen@iki.fi
Cheers
James
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
2017-11-28 11:04 ` James Hogan
2017-11-28 11:04 ` James Hogan
@ 2017-11-28 18:44 ` David Daney
1 sibling, 0 replies; 24+ messages in thread
From: David Daney @ 2017-11-28 18:44 UTC (permalink / raw)
To: James Hogan, David Daney; +Cc: Steven J. Hill, linux-mips, ralf
On 11/28/2017 03:04 AM, James Hogan wrote:
> Hi David,
>
> On Mon, Nov 27, 2017 at 10:56:33AM -0800, David Daney wrote:
>> On 11/13/2017 08:30 PM, Steven J. Hill wrote:
>>> From: "Steven J. Hill" <Steven.Hill@cavium.com>
>>>
>>> Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
>>> Acked-by: David Daney <david.daney@cavium.com>
>>> ---
>>> arch/mips/cavium-octeon/executive/cvmx-helper.c | 2 +-
>>> arch/mips/cavium-octeon/executive/cvmx-spi.c | 10 +++++-----
>>> arch/mips/include/asm/octeon/cvmx-fpa.h | 4 +++-
>>> arch/mips/include/asm/octeon/cvmx.h | 15 ++-------------
>>> arch/mips/pci/pcie-octeon.c | 12 ++++++------
>>> 5 files changed, 17 insertions(+), 26 deletions(-)
>>>
>>
>> WTF:
>>
>> drivers/staging/octeon-usb/octeon-hcd.c: In function 'cvmx_fifo_setup':
>> drivers/staging/octeon-usb/octeon-hcd.c:636:2: error: implicit
>> declaration of function 'cvmx_wait' [-Werror=implicit-function-declaration]
>> cc1: some warnings being treated as errors
>>
>> Why was this patch submitted and merged without running git-grep on
>> cvmx_wait?
>
> I guess I put too much store by your ack ;-)
>
> Lesson learned, I'll grep next time.
James,
I didn't intend to suggest that you are responsible for checking
things like that. Both you and I were fooled. It is the patch author
that I was hinting at that should be responsible for checking on things
like this.
>
>>
>> Steven, send a patch to fix the breakage.
>
> See this patch & thread which you were Cc'd on:
> https://lkml.kernel.org/r/20171117075010.24131-1-aaro.koskinen@iki.fi
>
> Cheers
> James
>
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2017-11-28 18:45 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-11-14 4:30 [PATCH v3 00/11] Add Octeon Hotplug CPU Support Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 01/11] MIPS: Add nudges to writes for bit unlocks Steven J. Hill
2017-11-14 15:39 ` Ralf Baechle
2017-11-14 15:43 ` Ralf Baechle
2017-11-14 17:57 ` David Daney
2017-11-14 4:30 ` [PATCH v3 02/11] MIPS: Remove unused variable 'lastpfn' Steven J. Hill
2017-11-14 15:40 ` Ralf Baechle
2017-11-14 4:30 ` [PATCH v3 03/11] MIPS: Allow __cpu_number_map to be larger than NR_CPUS Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 04/11] MIPS: Octeon: Remove usage of cvmx_wait() everywhere Steven J. Hill
2017-11-14 19:08 ` Ralf Baechle
2017-11-14 20:30 ` James Hogan
2017-11-14 20:30 ` James Hogan
2017-11-14 20:45 ` Ralf Baechle
2017-11-27 18:56 ` David Daney
2017-11-28 11:04 ` James Hogan
2017-11-28 11:04 ` James Hogan
2017-11-28 18:44 ` David Daney
2017-11-14 4:30 ` [PATCH v3 05/11] MIPS: Octeon: Header and file cleaning Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 06/11] MIPS: Octeon: Update values for CVMX_CIU_FUSE register Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 07/11] MIPS: Octeon: Add Octeon III platforms for console output Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 08/11] MIPS: Octeon: Remove crufty KEXEC and CRASH_DUMP code Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 09/11] MIPS: Octeon: Populate kernel memory from cvmx_bootmem named blocks Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 10/11] MIPS: Add the concept of BOOT_MEM_KERNEL to boot_mem_map Steven J. Hill
2017-11-14 4:30 ` [PATCH v3 11/11] MIPS: Octeon: Add working hotplug CPU support Steven J. Hill
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