[PATCH v5 0/1] MIPS: BCM47XX: Apply BCM5300X PCIe erratum workaround

[PATCH v5 0/1] MIPS: BCM47XX: Apply BCM5300X PCIe erratum workaround

[Tokunori Ikegami]

The workaround is to eanble ExternalSync mode and it is implemented on CFE.
But to enable this without CFE implemented it add the workaround into Linux.

Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org

Tokunori Ikegami (1):
  MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe
    erratum

 arch/mips/bcm47xx/setup.c        | 6 ++++++
 arch/mips/include/asm/mipsregs.h | 3 +++
 2 files changed, 9 insertions(+)

-- 
2.16.1

[PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe erratum

[Tokunori Ikegami]

The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as below.

  R10: PCIe Transactions Periodically Fail

    Description: The BCM5300X PCIe does not maintain transaction ordering.
                 This may cause PCIe transaction failure.
    Fix Comment: Add a dummy PCIe configuration read after a PCIe
                 configuration write to ensure PCIe configuration access
                 ordering. Set ES bit of CP0 configu7 register to enable
                 sync function so that the sync instruction is functional.
    Resolution:  hndpci.c: extpci_write_config()
                 hndmips.c: si_mips_init()
                 mipsinc.h CONF7_ES

This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
Also the dummy PCIe configuration read is already implemented in the Linux
BCMA driver.
Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
too so that the sync instruction is externalised.

Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
---
Changes since v4:
- Change Cc: Hauke Mehrtens tag as Acked-by tag.

Changes since v3:
- Add Reviewed-by: Paul Burton tag.
- Remove pr_info().

Changes since v2:
- Move the change into platform-specific code bcm47xx_cpu_fixes() function from in generic code.

Changes since v1 resent:
- None.

Changes since v1 original:
- Change to use set_c0_config7 instead of write_c0_config7.

 arch/mips/bcm47xx/setup.c        | 6 ++++++
 arch/mips/include/asm/mipsregs.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 6054d49e608e..8c9cbf13d32a 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -212,6 +212,12 @@ static int __init bcm47xx_cpu_fixes(void)
 		 */
 		if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
 			cpu_wait = NULL;
+
+		/*
+		 * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
+		 * Enable ExternalSync for sync instruction to take effect
+		 */
+		set_c0_config7(MIPS_CONF7_ES);
 		break;
 #endif
 	}
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 858752dac337..0f94acf60144 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -680,6 +680,8 @@
 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
+/* ExternalSync */
+#define MIPS_CONF7_ES		(_ULCAST_(1) << 8)
 
 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
@@ -2759,6 +2761,7 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
-- 
2.16.1

Re: [PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe erratum

[James Hogan]

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On Sun, Jun 03, 2018 at 11:02:01PM +0900, Tokunori Ikegami wrote:
> The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as below.
> 
>   R10: PCIe Transactions Periodically Fail
> 
>     Description: The BCM5300X PCIe does not maintain transaction ordering.
>                  This may cause PCIe transaction failure.
>     Fix Comment: Add a dummy PCIe configuration read after a PCIe
>                  configuration write to ensure PCIe configuration access
>                  ordering. Set ES bit of CP0 configu7 register to enable
>                  sync function so that the sync instruction is functional.
>     Resolution:  hndpci.c: extpci_write_config()
>                  hndmips.c: si_mips_init()
>                  mipsinc.h CONF7_ES
> 
> This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
> Also the dummy PCIe configuration read is already implemented in the Linux
> BCMA driver.
> Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
> too so that the sync instruction is externalised.
> 
> Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
> Reviewed-by: Paul Burton <paul.burton@mips.com>
> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Cc: Rafał Miłecki <zajec5@gmail.com>
> Cc: linux-mips@linux-mips.org

I presume this patch is ready to apply now (thanks for the reviews
folks).

How far back does this need backporting to stable branches?

It applies easily back to 3.14 I think (commit 3c06b12b046e ("MIPS:
BCM47XX: fix position of cpu_wait disabling")), but you mentioned other
fixes too. Have those been backported too, and if not is there any point
backporting this?

Thanks
James

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RE: [PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe erratum

[IKEGAMI Tokunori]

Hi James-san,

> I presume this patch is ready to apply now (thanks for the reviews
> folks).

  I am very happy with this. Thank you so much for your reviewing.

> How far back does this need backporting to stable branches?

  The patch is for maintenance purpose so better to apply stable branches.

> It applies easily back to 3.14 I think (commit 3c06b12b046e ("MIPS:
> BCM47XX: fix position of cpu_wait disabling")), but you mentioned other
> fixes too. Have those been backported too, and if not is there any point
> backporting this?

  Yes the other fixes also are possible to be applied to stable branches.
  The patches were reviewed as below and applied into the mtd/next branch.
    <https://patchwork.ozlabs.org/project/linux-mtd/list/?series=47464&state=*>
    <http://git.infradead.org/linux-mtd.git/shortlog/refs/heads/mtd/next>

  The patches 1/1 to 4/5 are tagged Cc: stable to apply into stable branches.
  But actually those have not been applied yet into stable branches I think.

Regards,
Ikegami

> -----Original Message-----
> From: James Hogan [mailto:jhogan@kernel.org]
> Sent: Wednesday, June 06, 2018 12:46 AM
> To: IKEGAMI Tokunori
> Cc: PACKHAM Chris; Rafał Miłecki; linux-mips@linux-mips.org
> Subject: Re: [PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core
> ExternalSync for BCM47XX PCIe erratum
> 
> On Sun, Jun 03, 2018 at 11:02:01PM +0900, Tokunori Ikegami wrote:
> > The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as
> below.
> >
> >   R10: PCIe Transactions Periodically Fail
> >
> >     Description: The BCM5300X PCIe does not maintain transaction
> ordering.
> >                  This may cause PCIe transaction failure.
> >     Fix Comment: Add a dummy PCIe configuration read after a PCIe
> >                  configuration write to ensure PCIe configuration
> access
> >                  ordering. Set ES bit of CP0 configu7 register to enable
> >                  sync function so that the sync instruction is
> functional.
> >     Resolution:  hndpci.c: extpci_write_config()
> >                  hndmips.c: si_mips_init()
> >                  mipsinc.h CONF7_ES
> >
> > This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
> > Also the dummy PCIe configuration read is already implemented in the Linux
> > BCMA driver.
> > Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
> > too so that the sync instruction is externalised.
> >
> > Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
> > Reviewed-by: Paul Burton <paul.burton@mips.com>
> > Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > Cc: Rafał Miłecki <zajec5@gmail.com>
> > Cc: linux-mips@linux-mips.org
> 
> I presume this patch is ready to apply now (thanks for the reviews
> folks).
> 
> How far back does this need backporting to stable branches?
> 
> It applies easily back to 3.14 I think (commit 3c06b12b046e ("MIPS:
> BCM47XX: fix position of cpu_wait disabling")), but you mentioned other
> fixes too. Have those been backported too, and if not is there any point
> backporting this?
> 
> Thanks
> James

RE: [PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe erratum

[IKEGAMI Tokunori]

Hi James-san,

Very sorry for too late to reply to your mail.
As reverted the patch already as you know no need to back port.
Again very sorry for the problem.

Regards,
Ikegami

> -----Original Message-----
> From: James Hogan [mailto:jhogan@kernel.org]
> Sent: Wednesday, June 06, 2018 12:46 AM
> To: IKEGAMI Tokunori
> Cc: PACKHAM Chris; Rafał Miłecki; linux-mips@linux-mips.org
> Subject: Re: [PATCH v5 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core
> ExternalSync for BCM47XX PCIe erratum
> 
> On Sun, Jun 03, 2018 at 11:02:01PM +0900, Tokunori Ikegami wrote:
> > The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as
> below.
> >
> >   R10: PCIe Transactions Periodically Fail
> >
> >     Description: The BCM5300X PCIe does not maintain transaction
> ordering.
> >                  This may cause PCIe transaction failure.
> >     Fix Comment: Add a dummy PCIe configuration read after a PCIe
> >                  configuration write to ensure PCIe configuration
> access
> >                  ordering. Set ES bit of CP0 configu7 register to enable
> >                  sync function so that the sync instruction is
> functional.
> >     Resolution:  hndpci.c: extpci_write_config()
> >                  hndmips.c: si_mips_init()
> >                  mipsinc.h CONF7_ES
> >
> > This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
> > Also the dummy PCIe configuration read is already implemented in the Linux
> > BCMA driver.
> > Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
> > too so that the sync instruction is externalised.
> >
> > Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
> > Reviewed-by: Paul Burton <paul.burton@mips.com>
> > Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > Cc: Rafał Miłecki <zajec5@gmail.com>
> > Cc: linux-mips@linux-mips.org
> 
> I presume this patch is ready to apply now (thanks for the reviews
> folks).
> 
> How far back does this need backporting to stable branches?
> 
> It applies easily back to 3.14 I think (commit 3c06b12b046e ("MIPS:
> BCM47XX: fix position of cpu_wait disabling")), but you mentioned other
> fixes too. Have those been backported too, and if not is there any point
> backporting this?
> 
> Thanks
> James