* [PATCH 4.16 006/279] MIPS: io: Prevent compiler reordering writeX()
[not found] <20180618080608.851973560@linuxfoundation.org>
@ 2018-06-18 8:09 ` Greg Kroah-Hartman
2018-06-18 8:09 ` [PATCH 4.16 013/279] MIPS: io: Add barrier after register read in readX() Greg Kroah-Hartman
2018-06-18 8:10 ` [PATCH 4.16 016/279] MIPS: dts: Boston: Fix PCI bus dtc warnings: Greg Kroah-Hartman
2 siblings, 0 replies; 3+ messages in thread
From: Greg Kroah-Hartman @ 2018-06-18 8:09 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Sinan Kaya, Arnd Bergmann,
Ralf Baechle, Paul Burton, linux-mips, James Hogan, Sasha Levin
4.16-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sinan Kaya <okaya@codeaurora.org>
[ Upstream commit f6b7aeee8f167409195fbf1364d02988fecad1d0 ]
writeX() has strong ordering semantics with respect to memory updates.
In the absence of a write barrier or a compiler barrier, the compiler
can reorder register and memory update instructions. This breaks the
writeX() API.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18997/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -307,7 +307,7 @@ static inline void iounmap(const volatil
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
-#define war_io_reorder_wmb() do { } while (0)
+#define war_io_reorder_wmb() barrier()
#endif
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 4.16 013/279] MIPS: io: Add barrier after register read in readX()
[not found] <20180618080608.851973560@linuxfoundation.org>
2018-06-18 8:09 ` [PATCH 4.16 006/279] MIPS: io: Prevent compiler reordering writeX() Greg Kroah-Hartman
@ 2018-06-18 8:09 ` Greg Kroah-Hartman
2018-06-18 8:10 ` [PATCH 4.16 016/279] MIPS: dts: Boston: Fix PCI bus dtc warnings: Greg Kroah-Hartman
2 siblings, 0 replies; 3+ messages in thread
From: Greg Kroah-Hartman @ 2018-06-18 8:09 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Sinan Kaya, Arnd Bergmann,
Ralf Baechle, Paul Burton, linux-mips, James Hogan, Sasha Levin
4.16-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sinan Kaya <okaya@codeaurora.org>
[ Upstream commit a1cc7034e33d12dc17d13fbcd7d597d552889097 ]
While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA data prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 4.16 016/279] MIPS: dts: Boston: Fix PCI bus dtc warnings:
[not found] <20180618080608.851973560@linuxfoundation.org>
2018-06-18 8:09 ` [PATCH 4.16 006/279] MIPS: io: Prevent compiler reordering writeX() Greg Kroah-Hartman
2018-06-18 8:09 ` [PATCH 4.16 013/279] MIPS: io: Add barrier after register read in readX() Greg Kroah-Hartman
@ 2018-06-18 8:10 ` Greg Kroah-Hartman
2 siblings, 0 replies; 3+ messages in thread
From: Greg Kroah-Hartman @ 2018-06-18 8:10 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Matt Redfearn, Ralf Baechle,
Paul Burton, Rob Herring, Mark Rutland, linux-mips, devicetree,
James Hogan, Sasha Levin
4.16-stable review patch. If anyone has any objections, please let me know.
------------------
From: Matt Redfearn <matt.redfearn@mips.com>
[ Upstream commit 2c2bf522ed8cbfaac666f7dc65cfd38de2b89f0f ]
dtc recently (v1.4.4-8-g756ffc4f52f6) added PCI bus checks. Fix the
warnings now emitted:
arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@10000000: missing bus-range for PCI bridge
arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@12000000: missing bus-range for PCI bridge
arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@14000000: missing bus-range for PCI bridge
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/19070/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/boot/dts/img/boston.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/mips/boot/dts/img/boston.dts
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -51,6 +51,8 @@
ranges = <0x02000000 0 0x40000000
0x40000000 0 0x40000000>;
+ bus-range = <0x00 0xff>;
+
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pci0_intc 1>,
<0 0 0 2 &pci0_intc 2>,
@@ -79,6 +81,8 @@
ranges = <0x02000000 0 0x20000000
0x20000000 0 0x20000000>;
+ bus-range = <0x00 0xff>;
+
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pci1_intc 1>,
<0 0 0 2 &pci1_intc 2>,
@@ -107,6 +111,8 @@
ranges = <0x02000000 0 0x16000000
0x16000000 0 0x100000>;
+ bus-range = <0x00 0xff>;
+
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pci2_intc 1>,
<0 0 0 2 &pci2_intc 2>,
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-06-18 8:09 ` [PATCH 4.16 006/279] MIPS: io: Prevent compiler reordering writeX() Greg Kroah-Hartman
2018-06-18 8:09 ` [PATCH 4.16 013/279] MIPS: io: Add barrier after register read in readX() Greg Kroah-Hartman
2018-06-18 8:10 ` [PATCH 4.16 016/279] MIPS: dts: Boston: Fix PCI bus dtc warnings: Greg Kroah-Hartman
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