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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Lichao Liu <liulichao@loongson.cn>,
	Paul Burton <paulburton@kernel.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Max Filippov <jcmvbkbc@gmail.com>,
	yuanjunqing@loongson.cn, linux-mips@vger.kernel.org
Subject: Re: [PATCH] MIPS: CPU_LOONGSON2EF need software to maintain cache consistency
Date: Tue, 26 May 2020 18:00:45 +0200	[thread overview]
Message-ID: <20200526160045.GA12325@alpha.franken.de> (raw)
In-Reply-To: <20200526232556.14a40f6c@halation.net.flygoat.com>

On Tue, May 26, 2020 at 11:25:56PM +0800, Jiaxun Yang wrote:
> On Tue, 26 May 2020 14:29:50 +0100
> Robin Murphy <robin.murphy@arm.com> wrote:
> 
> > On 2020-05-26 14:01, Thomas Bogendoerfer wrote:
> > > On Tue, May 26, 2020 at 08:40:28PM +0800, Lichao Liu wrote:  
> > >> Loongson-2EF need software maintain cache consistency, So when
> > >> using streaming DMA, software needs to maintain consistency.
> > >>
> > >> dma_map_single() is correct, but dma_unmap_single is wrong.
> > >>
> > >> The function call path:
> > >> 'dma_unmap_single->dma_unmap_page_attrs->dma_direct_unmap_page->
> > >>   dma_direct_sync_single_for_cpu->arch_sync_dma_for_cpu->
> > >>   cpu_needs_post_dma_flush'
> > >>
> > >> In current version, 'cpu_needs_post_dma_flush' will return false
> > >> at Loongon-2EF platform, and dma_unmap_single will not invalidate
> > >> cache, driver may access wrong dma data.  
> > > 
> > > why should it ? CPU must not touch data while it's mapped for DMA.
> > >   
> > >> I don't know what's the exact meaning of "fill random cachelines
> > >> with stale data at any time". I always think
> > >> 'cpu_needs_post_dma_flush()' means whether this platform needs
> > >> software to maintain cache consistency.  
> > > 
> > > this will only happen, if cpu speculates creates dirty cache lines
> > > by speculation as R10k type of CPUs do.  
> > 
> > Will it? The usual pattern for this problem is that the CPU 
> > speculatively fills a (clean) cache line after a DMA_FROM_DEVICE 
> > operation has begun, but before the device has actually written to
> > that part of the buffer. Thus a subsequent CPU read after the
> > operation is complete can hit in the cache and return the previous
> > data rather than the updated data that the device wrote. I don't know
> > about MIPS specifically, but that can certainly happen on Arm.
> 
> Checked the manual of Loongson-2F again and I must admit the case may
> happen on Loongson-2EF processor.

so the patch is correct ?
> 
> R4k manual didn't show the details of speculative policy but I think
> that should be applied to all R4k like processors?

R4k doesn't speculate at all.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

  reply	other threads:[~2020-05-26 16:16 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-26 11:14 [PATCH] MIPS: CPU_LOONGSON2EF need software to maintain cache consistency Lichao Liu
2020-05-26 11:38 ` Jiaxun Yang
2020-05-26 12:40   ` Lichao Liu
2020-05-26 13:01     ` Thomas Bogendoerfer
2020-05-26 13:29       ` Robin Murphy
2020-05-26 15:01         ` Lichao Liu
2020-05-26 15:25         ` Jiaxun Yang
2020-05-26 16:00           ` Thomas Bogendoerfer [this message]
2020-05-26 16:42             ` Jiaxun Yang
2020-05-26 16:16         ` Thomas Bogendoerfer
2020-05-26 13:25     ` Jiaxun Yang
2020-05-26 14:50       ` Lichao Liu
2020-05-27 10:49 ` Thomas Bogendoerfer
  -- strict thread matches above, loose matches on Subject: below --
2020-05-28  1:10 Lichao Liu
2020-05-28  6:05 ` Jiaxun Yang
2020-05-28  7:44 ` Thomas Bogendoerfer

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