Re: [PATCH] MIPS: CPU_LOONGSON2EF need software to maintain cache consistency

[Jiaxun Yang <jiaxun.yang@flygoat.com>]

On Tue, 26 May 2020 19:14:38 +0800
Lichao Liu <liulichao@loongson.cn> wrote:

> CPU_LOONGSON2EF need software to maintain cache consistency,
> so modify the 'cpu_needs_post_dma_flush' function to return true
> when the cpu type is CPU_LOONGSON2EF.


Hi Lichao,

I don't think that's required for Loongson-2EF,

According to the comment in code:

The affected CPUs below in 'cpu_needs_post_dma_flush()' can
speculatively
fill random cachelines with stale data at any time, requiring an
extra flush post-DMA.

And according to my understanding that's not going to happen on
Loongson-2EF. We're always allocating coherent DMA memory in uncached
range, Loongson-2EF's writeback policy will ensure it won't writeback
random lines to the memory but only modified dirty lines.

We've been fine without post flush for almost 10 years, there is no
stability issue revealed.

Btw: Please keep me CCed for Loongson-2EF patches. I'm not very active
on 2EF development but I'll still review patches.

Thanks.


> ---
>  arch/mips/mm/dma-noncoherent.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/mips/mm/dma-noncoherent.c
> b/arch/mips/mm/dma-noncoherent.c index fcea92d95d86..563c2c0d0c81
> 100644 --- a/arch/mips/mm/dma-noncoherent.c
> +++ b/arch/mips/mm/dma-noncoherent.c
> @@ -33,6 +33,7 @@ static inline bool cpu_needs_post_dma_flush(void)
>  	case CPU_R10000:
>  	case CPU_R12000:
>  	case CPU_BMIPS5000:
> +	case CPU_LOONGSON2EF:
>  		return true;
>  	default:
>  		/*
--
Jiaxun Yang