[PATCH 1/2] dt-bindings: mips: lantiq: Document Lantiq Xway GPTU

[PATCH 1/2] dt-bindings: mips: lantiq: Document Lantiq Xway GPTU

[Aleksander Jan Bajkowski]

The Lantiq SoC has six built-in 16-bit general purpose timers (GPTU).

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 .../mips/lantiq/lantiq,gptu-xway.yaml         | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml

diff --git a/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
new file mode 100644
index 000000000000..fcfc634dd391
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/lantiq/lantiq,gptu-xway.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq Xway SoC series General Purpose Timer Unit (GPTU)
+
+maintainers:
+  - Aleksander Jan Bajkowski <olek2@wp.pl>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - lantiq,gptu-xway
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 6
+    maxItems: 6
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    gptu@e100a00 {
+        compatible = "lantiq,gptu-xway";
+        reg = <0xe100a00 0x100>;
+        interrupt-parent = <&icu0>;
+        interrupts = <126>, <127>, <128>, <129> ,<130>, <131>;
+    };
-- 
2.47.2

[PATCH 2/2] mips: lantiq: danube: add missing timer interrupts

[Aleksander Jan Bajkowski]

The driver expects six interrupt lines to be specified.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 arch/mips/boot/dts/lantiq/danube.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi
index 7a7ba66aa534..371d06d1a225 100644
--- a/arch/mips/boot/dts/lantiq/danube.dtsi
+++ b/arch/mips/boot/dts/lantiq/danube.dtsi
@@ -71,6 +71,8 @@ fpi@10000000 {
 		gptu@e100a00 {
 			compatible = "lantiq,gptu-xway";
 			reg = <0xe100a00 0x100>;
+			interrupt-parent = <&icu0>;
+			interrupts = <126 127 128 129 130 131>;
 		};
 
 		serial@e100c00 {
-- 
2.47.2

Re: [PATCH 1/2] dt-bindings: mips: lantiq: Document Lantiq Xway GPTU

[Conor Dooley]

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On Thu, Aug 14, 2025 at 11:36:59AM +0200, Aleksander Jan Bajkowski wrote:
> The Lantiq SoC has six built-in 16-bit general purpose timers (GPTU).
> 
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> ---
>  .../mips/lantiq/lantiq,gptu-xway.yaml         | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> new file mode 100644
> index 000000000000..fcfc634dd391
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/lantiq/lantiq,gptu-xway.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lantiq Xway SoC series General Purpose Timer Unit (GPTU)

"SoC series" implies that you're using the same compatible for multiple
devices. Why are you not using device-specific compatibles?

> +
> +maintainers:
> +  - Aleksander Jan Bajkowski <olek2@wp.pl>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - lantiq,gptu-xway
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 6
> +    maxItems: 6

And these interrupts are what exactly? I'd rather an items list
explaining what they are tbh.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    gptu@e100a00 {
> +        compatible = "lantiq,gptu-xway";
> +        reg = <0xe100a00 0x100>;
> +        interrupt-parent = <&icu0>;
> +        interrupts = <126>, <127>, <128>, <129> ,<130>, <131>;
> +    };
> -- 
> 2.47.2
> 

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Re: [PATCH 1/2] dt-bindings: mips: lantiq: Document Lantiq Xway GPTU

[Aleksander Jan Bajkowski]

On 8/14/25 22:50, Conor Dooley wrote:
> On Thu, Aug 14, 2025 at 11:36:59AM +0200, Aleksander Jan Bajkowski wrote:
>> The Lantiq SoC has six built-in 16-bit general purpose timers (GPTU).
>>
>> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
>> ---
>>   .../mips/lantiq/lantiq,gptu-xway.yaml         | 39 +++++++++++++++++++
>>   1 file changed, 39 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
>> new file mode 100644
>> index 000000000000..fcfc634dd391
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
>> @@ -0,0 +1,39 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mips/lantiq/lantiq,gptu-xway.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Lantiq Xway SoC series General Purpose Timer Unit (GPTU)
> "SoC series" implies that you're using the same compatible for multiple
> devices. Why are you not using device-specific compatibles?

This IP Core didn't change in subsequent generations of SoCs, so it had
one compatible string. In the next iteration, I will add device-specific
compatibles.

Re: [PATCH 1/2] dt-bindings: mips: lantiq: Document Lantiq Xway GPTU

[Conor Dooley]

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On Sat, Aug 16, 2025 at 02:04:09PM +0200, Aleksander Jan Bajkowski wrote:
> 
> On 8/14/25 22:50, Conor Dooley wrote:
> > On Thu, Aug 14, 2025 at 11:36:59AM +0200, Aleksander Jan Bajkowski wrote:
> > > The Lantiq SoC has six built-in 16-bit general purpose timers (GPTU).
> > > 
> > > Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> > > ---
> > >   .../mips/lantiq/lantiq,gptu-xway.yaml         | 39 +++++++++++++++++++
> > >   1 file changed, 39 insertions(+)
> > >   create mode 100644 Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> > > new file mode 100644
> > > index 000000000000..fcfc634dd391
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mips/lantiq/lantiq,gptu-xway.yaml
> > > @@ -0,0 +1,39 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/mips/lantiq/lantiq,gptu-xway.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Lantiq Xway SoC series General Purpose Timer Unit (GPTU)
> > "SoC series" implies that you're using the same compatible for multiple
> > devices. Why are you not using device-specific compatibles?
> 
> This IP Core didn't change in subsequent generations of SoCs, so it had
> one compatible string. In the next iteration, I will add device-specific
> compatibles.

You can (and should) use a fallback when you do that, probably to
whatever the first device to contain the IP is. The driver need only
contain the one fallback compatible.

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