From: Jun Sun <jsun@mvista.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr, ralf@oss.sgi.com
Subject: Re: PROPOSAL : multi-way cache support in Linux/MIPS
Date: Wed, 02 Aug 2000 16:10:43 -0700 [thread overview]
Message-ID: <3988AA72.5C342E1D@mvista.com> (raw)
In-Reply-To: 027f01bffcd3$3279b800$0deca8c0@Ulysses
That certainly helps a lot. Thanks, Kevin.
"Kevin D. Kissell" wrote:
...
>
> So, to get back to Linux, a MIPS32 part can *almost*
> run the standard MIPS R4K kernel. Almost. What had
Still one more question. If I understand correctly, the 4Km and 4Kp are
MIPS32 CPUs. However, they don't have TLBs. Right? Without TLBs, I
don't suppose Linux will run ...
Jun
next prev parent reply other threads:[~2000-08-02 23:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-08-02 22:44 PROPOSAL : multi-way cache support in Linux/MIPS Kevin D. Kissell
2000-08-02 22:44 ` Kevin D. Kissell
2000-08-02 23:10 ` Jun Sun [this message]
2000-08-02 23:31 ` Ralf Baechle
-- strict thread matches above, loose matches on Subject: below --
2000-08-02 18:36 Kevin D. Kissell
2000-08-02 18:36 ` Kevin D. Kissell
2000-08-02 18:15 Kevin D. Kissell
2000-08-02 18:15 ` Kevin D. Kissell
2000-08-02 21:50 ` Jun Sun
2000-08-02 8:26 Kevin D. Kissell
2000-08-02 8:26 ` Kevin D. Kissell
2000-08-02 17:05 ` Jun Sun
2000-08-01 23:52 Jun Sun
2000-08-02 18:12 ` Dominic Sweetman
2000-08-02 21:38 ` Jun Sun
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