Re: yosemite interrupt setup

[Manish Lachwani <mlachwani@mvista.com>]

Thomas Koeller wrote:

>Hi Manish,
>
>may I ask you to help me with this:
>
>I am currently analyzing the yosemite interrupt handling
>code. So far I have not been able to find the point
>where the association between a particular external or
>message interrupt and its vector is established. It seems
>that the corresponding OCD address definitions from
>asm-mips/titan_dep.h, such as RM9000x2_OCD_INTPIN0, are
>not used anywhere in the code. I guess the kernel does
>not rely on PMON having set up this before, or does it?
>
>thanks,
>Thomas
>
>  
>
Hi Thomas

As far as I remember, the message interrupts can be invoked by writing 
to the INTMSG register. Are you referring to the Hypertransport section 
or the ethernet section? No, PMON does not do any interrupt related 
setup. All that is done in Linux.

For example, if you look at the titan ge driver, there is a section:

	/*
	 * Enable the Interrupts for Tx and Rx
	 */
	reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);

	if (port_num == 0) {
		reg_data1 |= 0x3;
#ifdef CONFIG_SMP
		TITAN_GE_WRITE(0x0038, 0x003);
#else
		TITAN_GE_WRITE(0x0038, 0x303);
#endif
	}

	if (port_num == 1) {
		reg_data1 |= 0x300;
	}

	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
	TITAN_GE_WRITE(0x003c, 0x300);

	if (config_done == 0) {
		TITAN_GE_WRITE(0x0024, 0x04000024);	/* IRQ vector */
		TITAN_GE_WRITE(0x0020, 0x000fb000);	/* INTMSG base */
	}


Here, 0xfb000020 is the INTMSG register. And 0xfb000024 is the Interrupt Vector register. 

AFAIK, the IRQ vector is 8 bits with the top three bits signifying the interrupt number and 
the bottom three bits indicates the 32 interrupt status bits. So, essentially there are 256 message
interrupts.

Let me know if this helps or if there is something specific ...

Thanks
Manish Lachwani