yosemite interrupt setup

yosemite interrupt setup

[Thomas Koeller]

Hi Manish,

may I ask you to help me with this:

I am currently analyzing the yosemite interrupt handling
code. So far I have not been able to find the point
where the association between a particular external or
message interrupt and its vector is established. It seems
that the corresponding OCD address definitions from
asm-mips/titan_dep.h, such as RM9000x2_OCD_INTPIN0, are
not used anywhere in the code. I guess the kernel does
not rely on PMON having set up this before, or does it?

thanks,
Thomas

-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

Re: yosemite interrupt setup

[Manish Lachwani]

Thomas Koeller wrote:

>Hi Manish,
>
>may I ask you to help me with this:
>
>I am currently analyzing the yosemite interrupt handling
>code. So far I have not been able to find the point
>where the association between a particular external or
>message interrupt and its vector is established. It seems
>that the corresponding OCD address definitions from
>asm-mips/titan_dep.h, such as RM9000x2_OCD_INTPIN0, are
>not used anywhere in the code. I guess the kernel does
>not rely on PMON having set up this before, or does it?
>
>thanks,
>Thomas
>
>  
>
Hi Thomas

As far as I remember, the message interrupts can be invoked by writing 
to the INTMSG register. Are you referring to the Hypertransport section 
or the ethernet section? No, PMON does not do any interrupt related 
setup. All that is done in Linux.

For example, if you look at the titan ge driver, there is a section:

	/*
	 * Enable the Interrupts for Tx and Rx
	 */
	reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);

	if (port_num == 0) {
		reg_data1 |= 0x3;
#ifdef CONFIG_SMP
		TITAN_GE_WRITE(0x0038, 0x003);
#else
		TITAN_GE_WRITE(0x0038, 0x303);
#endif
	}

	if (port_num == 1) {
		reg_data1 |= 0x300;
	}

	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
	TITAN_GE_WRITE(0x003c, 0x300);

	if (config_done == 0) {
		TITAN_GE_WRITE(0x0024, 0x04000024);	/* IRQ vector */
		TITAN_GE_WRITE(0x0020, 0x000fb000);	/* INTMSG base */
	}


Here, 0xfb000020 is the INTMSG register. And 0xfb000024 is the Interrupt Vector register. 

AFAIK, the IRQ vector is 8 bits with the top three bits signifying the interrupt number and 
the bottom three bits indicates the 32 interrupt status bits. So, essentially there are 256 message
interrupts.

Let me know if this helps or if there is something specific ...

Thanks
Manish Lachwani

Re: yosemite interrupt setup

[Manish Lachwani]

Manish Lachwani wrote:

> Thomas Koeller wrote:
>
>> Hi Manish,
>>
>> may I ask you to help me with this:
>>
>> I am currently analyzing the yosemite interrupt handling
>> code. So far I have not been able to find the point
>> where the association between a particular external or
>> message interrupt and its vector is established. It seems
>> that the corresponding OCD address definitions from
>> asm-mips/titan_dep.h, such as RM9000x2_OCD_INTPIN0, are
>> not used anywhere in the code. I guess the kernel does
>> not rely on PMON having set up this before, or does it?
>>
>> thanks,
>> Thomas
>>
>>  
>>
> Hi Thomas
>
> As far as I remember, the message interrupts can be invoked by writing 
> to the INTMSG register. Are you referring to the Hypertransport 
> section or the ethernet section? No, PMON does not do any interrupt 
> related setup. All that is done in Linux.
>
> For example, if you look at the titan ge driver, there is a section:
>
>     /*
>      * Enable the Interrupts for Tx and Rx
>      */
>     reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
>
>     if (port_num == 0) {
>         reg_data1 |= 0x3;
> #ifdef CONFIG_SMP
>         TITAN_GE_WRITE(0x0038, 0x003);
> #else
>         TITAN_GE_WRITE(0x0038, 0x303);
> #endif
>     }
>
>     if (port_num == 1) {
>         reg_data1 |= 0x300;
>     }
>
>     TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
>     TITAN_GE_WRITE(0x003c, 0x300);
>
>     if (config_done == 0) {
>         TITAN_GE_WRITE(0x0024, 0x04000024);    /* IRQ vector */
>         TITAN_GE_WRITE(0x0020, 0x000fb000);    /* INTMSG base */
>     }
>
>
> Here, 0xfb000020 is the INTMSG register. And 0xfb000024 is the 
> Interrupt Vector register.
> AFAIK, the IRQ vector is 8 bits with the top three bits signifying the 
> interrupt number and the bottom three bits indicates the 32 interrupt 
> status bits. So, essentially there are 256 message
> interrupts.
>
> Let me know if this helps or if there is something specific ...
>
> Thanks
> Manish Lachwani
>
>
>
>
>
Hi Thomas

Let me correct myself: 0xfe000020 is the INTMSG base register and 
0xfe000024 is the Interrupt Vector register (for the ethernet block). 
The actual INTMSG register resides in 0xfb000a00. Another example is 
arch/mips/pmc-sierra/yosemite/smp.c where an interrupt is generated by 
writing a vector to the INTMSG register:

 *(volatile uint32_t *)(0xfb000a00) = 0x00610002;

Thanks
Manish Lachwani

Re: yosemite interrupt setup

[Thomas Koeller]

On Wednesday 20 October 2004 20:13, Manish Lachwani wrote:

>         TITAN_GE_WRITE(0x0024, 0x04000024);    /* IRQ vector */
>         TITAN_GE_WRITE(0x0020, 0x000fb000);    /* INTMSG base */

Hi Manish,

it was the location of these two lines that I was asking for. So they
are in the ethernet driver. Wouldn't you agree that they should go
into the platform instead? The interrrupt is shared with
other devices, the DUART to name just one example, and if I want to
write a driver for these, then that driver would depend on the
ethernet driver, if that does the interrupt setup.

So this covers the message interrupts, but I also have not been
able so far to spot the location where the corresponding setup
is done for the external interrupt lines, that is, setting up
the INTPINx registers. Any hints?

thank you,
Thomas

-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

Re: yosemite interrupt setup

[Manish Lachwani]

Thomas Koeller wrote:
> On Wednesday 20 October 2004 20:13, Manish Lachwani wrote:
> 
> 
>>        TITAN_GE_WRITE(0x0024, 0x04000024);    /* IRQ vector */
>>        TITAN_GE_WRITE(0x0020, 0x000fb000);    /* INTMSG base */
> 
> 
> Hi Manish,
> 
> it was the location of these two lines that I was asking for. So they
> are in the ethernet driver. Wouldn't you agree that they should go
> into the platform instead? The interrrupt is shared with
> other devices, the DUART to name just one example, and if I want to
> write a driver for these, then that driver would depend on the
> ethernet driver, if that does the interrupt setup.
> 
> So this covers the message interrupts, but I also have not been
> able so far to spot the location where the corresponding setup
> is done for the external interrupt lines, that is, setting up
> the INTPINx registers. Any hints?
> 
> thank you,
> Thomas
> 

Hi Thomas

No, these should remain in the Ethernet driver. Thats because no other 
driver depends on these. Those registers are MAC subsystem registers 
only. The ethernet driver does not do any interrupt setup for other 
devices. Lets take these registers one by one:

TITAN_GE_WRITE(0x0024, 0x04000024);    /* IRQ vector */

This register is to tell the MAC subsystem what IRQ vectors to use. If 
you dont configure this register, only the MAC subsystem cannot send 
interrupts to the processor. But, thats abt it.

TITAN_GE_WRITE(0x0020, 0x000fb000);    /* INTMSG base */

This register tells the MAC subsystem only where the INTMSG base is. So, 
if the MAC subsystem needs to send an interrupt, it can write the IRQ 
vector to the INTMSG register and uses this register to find the base of 
the INTMSG register. Thats all. If you dont configure this register, 
then only the MAC subsystem cannot send interrupts.

As far as external interrupts go, I think include/asm-mips/serial.h 
should indicate the serial interrupt used and 
arch/mips/pmc-sierra/yosemite/pci-irq.c should indicate the IRQ line 
that PCI uses. HT and MAC are based off message interrupts. If you are 
using Titan native UART, it is also based off message interrupts. And 
the interrupt config is done in arch/mips/pmc-sierra/yosemite/irq.c.

Is this what you wanted to know abt setting up the external interrupt lines?

Thanks
Manish Lachwani

Re: yosemite interrupt setup

[Thomas Koeller]

On Thursday 21 October 2004 18:38, Manish Lachwani wrote:
> Hi Thomas
>
> No, these should remain in the Ethernet driver. Thats because no other
> driver depends on these. Those registers are MAC subsystem registers
> only. The ethernet driver does not do any interrupt setup for other
> devices.

Hi Manish,

first of all, forget about the yosemite, as I am no longer using it. I
am currently working on our own platform port.

All the components of the Ethernet/GPI subsystem interrupt the CPU
through the interrupt vector established by writing to the CPCFG0 and
CPCFG1 registers. So if I want to write a driver that uses one of
the GPIs, or the DUART, or a watchdog counter, or the two-bit interface,
or any other component of the subsystem, then this driver will be
dependent of the ethernet driver. Have a look at the manual if
you do not believe me. The titan ethernet driver is the only one to
use this interrupt _on_the_yosemite_, but this is only because all the
other components are not used at all.

The interrupt setup should definitly be in the platform - please reconsider
your position.

thanks,
Thomas

-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

Re: yosemite interrupt setup

[Manish Lachwani]

Hi Thomas,

Thomas Koeller wrote:
> On Thursday 21 October 2004 18:38, Manish Lachwani wrote:
> 
>>Hi Thomas
>>
>>No, these should remain in the Ethernet driver. Thats because no other
>>driver depends on these. Those registers are MAC subsystem registers
>>only. The ethernet driver does not do any interrupt setup for other
>>devices.
> 
> 
> Hi Manish,
> 
> first of all, forget about the yosemite, as I am no longer using it. I
> am currently working on our own platform port.

I did not know abt this. I have referred to Yosemite in the past posts

> 
> All the components of the Ethernet/GPI subsystem interrupt the CPU
> through the interrupt vector established by writing to the CPCFG0 and
> CPCFG1 registers. So if I want to write a driver that uses one of
> the GPIs, or the DUART, or a watchdog counter, or the two-bit interface,
> or any other component of the subsystem, then this driver will be
> dependent of the ethernet driver. Have a look at the manual if
> you do not believe me. The titan ethernet driver is the only one to
> use this interrupt _on_the_yosemite_, but this is only because all the
> other components are not used at all.

I will check the manual and get back. In case of Yosemite, the GE unit 
is the only one using this vector register.

> 
> The interrupt setup should definitly be in the platform - please reconsider
> your position.
> 
> thanks,
> Thomas
> 

Thanks
Manish Lachwani