Some cache questions

Some cache questions

[Thomas Petazzoni]

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Hello,

I'm using an RM9000 dual-core processor, buggy revisions (the one that 
doesn't support the "Shared" cache state if I understood correctly).

When going through the CVS logs, I saw that Ralf quite recently changed 
the cache mode from 4 to 5 in pgtable-bits.h. Is that change involved in 
the use of the "Shared" cache state with newer RM9000 revisions that 
don't have the bug ?

Currently, the KSEG0 cache coherency mode (2 lower bits of the CONFIG 
register) is set to 3 during PMON (start.S file). When I write something 
to the memory through KSEG0 with the first core, it doesn't appear to be 
read by the second core. This indicates, in my opinion, that the cache 
line of the first core hasn't been written to memory so that the second 
core could use it. Am I right ?

If I want to correctly use both cores using KSEG0, should I set the mode 
in the CONFIG register to 4 (so that I can work with buggy processors) ?

Thanks,

Thomas
-- 
PETAZZONI Thomas - thomas.petazzoni@enix.org
http://thomas.enix.org - Jabber: thomas.petazzoni@jabber.dk
http://kos.enix.org, http://sos.enix.org
Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E  1624 F653 CB30 98D3 F7A7

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RE: Some cache questions

[Brad Larson]

You haven't mentioned which board.  If its Yosemite then you may have one of the few not upgraded to 1.2 silicon.  If so it won't work with the changes committed by Ralf which requires the shared state for SMP boot.  For further discussion contact the apps@pmc-sierra.com

--Brad

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Thomas Petazzoni
Sent: Monday, December 27, 2004 8:35 AM
To: linux-mips@linux-mips.org
Subject: Some cache questions


Hello,

I'm using an RM9000 dual-core processor, buggy revisions (the one that 
doesn't support the "Shared" cache state if I understood correctly).

When going through the CVS logs, I saw that Ralf quite recently changed 
the cache mode from 4 to 5 in pgtable-bits.h. Is that change involved in 
the use of the "Shared" cache state with newer RM9000 revisions that 
don't have the bug ?

Currently, the KSEG0 cache coherency mode (2 lower bits of the CONFIG 
register) is set to 3 during PMON (start.S file). When I write something 
to the memory through KSEG0 with the first core, it doesn't appear to be 
read by the second core. This indicates, in my opinion, that the cache 
line of the first core hasn't been written to memory so that the second 
core could use it. Am I right ?

If I want to correctly use both cores using KSEG0, should I set the mode 
in the CONFIG register to 4 (so that I can work with buggy processors) ?

Thanks,

Thomas
-- 
PETAZZONI Thomas - thomas.petazzoni@enix.org
http://thomas.enix.org - Jabber: thomas.petazzoni@jabber.dk
http://kos.enix.org, http://sos.enix.org
Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E  1624 F653 CB30 98D3 F7A7

RE: Some cache questions

[Manish Lachwani]

Hello !

For chip revisions 1.0 and 1.1, there are some changes
to the memory management subsystem for the kernel to
work on the board (dual core). As already known, these
versions dont support Shared state.

I had made those changes to the 2.4.21 kernel. Maybe
you can take a look at those changes and port them to
2.6 appropriately. However, there is more sanity in
1.2 version

Thanks
Manish Lachwani


--- Brad Larson <Brad_Larson@pmc-sierra.com> wrote:

> You haven't mentioned which board.  If its Yosemite
> then you may have one of the few not upgraded to 1.2
> silicon.  If so it won't work with the changes
> committed by Ralf which requires the shared state
> for SMP boot.  For further discussion contact the
> apps@pmc-sierra.com
> 
> --Brad
> 
> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org
> [mailto:linux-mips-bounce@linux-mips.org]On Behalf
> Of Thomas Petazzoni
> Sent: Monday, December 27, 2004 8:35 AM
> To: linux-mips@linux-mips.org
> Subject: Some cache questions
> 
> 
> Hello,
> 
> I'm using an RM9000 dual-core processor, buggy
> revisions (the one that 
> doesn't support the "Shared" cache state if I
> understood correctly).
> 
> When going through the CVS logs, I saw that Ralf
> quite recently changed 
> the cache mode from 4 to 5 in pgtable-bits.h. Is
> that change involved in 
> the use of the "Shared" cache state with newer
> RM9000 revisions that 
> don't have the bug ?
> 
> Currently, the KSEG0 cache coherency mode (2 lower
> bits of the CONFIG 
> register) is set to 3 during PMON (start.S file).
> When I write something 
> to the memory through KSEG0 with the first core, it
> doesn't appear to be 
> read by the second core. This indicates, in my
> opinion, that the cache 
> line of the first core hasn't been written to memory
> so that the second 
> core could use it. Am I right ?
> 
> If I want to correctly use both cores using KSEG0,
> should I set the mode 
> in the CONFIG register to 4 (so that I can work with
> buggy processors) ?
> 
> Thanks,
> 
> Thomas
> -- 
> PETAZZONI Thomas - thomas.petazzoni@enix.org
> http://thomas.enix.org - Jabber:
> thomas.petazzoni@jabber.dk
> http://kos.enix.org, http://sos.enix.org
> Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E  1624 F653
> CB30 98D3 F7A7
> 
> 

Re: Some cache questions

[Thomas Petazzoni]

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Hello,

Manish Lachwani a écrit :

> For chip revisions 1.0 and 1.1, there are some changes
> to the memory management subsystem for the kernel to
> work on the board (dual core). As already known, these
> versions dont support Shared state.
> 
> I had made those changes to the 2.4.21 kernel. Maybe
> you can take a look at those changes and port them to
> 2.6 appropriately. However, there is more sanity in
> 1.2 version

Actually, my question was not really Linux-specific. On the second core, 
I will not use the MMU, because this core will not run Linux, but a 
custom code. Both cores will share informations through KSEG0, so I need 
to maintain coherency between caches. What should I do in order to do 
that ? Is it enough to set cache mode for KSEG0 to 4 (in the CONFIG 
register) ?

I have only 1.0 and 1.1 cores, on home-made boards, so there's no way to 
switch to 1.2.

BTW, do you have pointers, papers, information about a system running 
Linux on a core, and some custom code on a second core, in order to have 
real-time on the second core with very low latency ?

Thanks,

Thomas
-- 
PETAZZONI Thomas - thomas.petazzoni@enix.org
http://thomas.enix.org - Jabber: thomas.petazzoni@jabber.dk
http://kos.enix.org, http://sos.enix.org
Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E  1624 F653 CB30 98D3 F7A7

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