Au1550 system bus masters issue

Au1550 system bus masters issue

[David Sanchez]

Hi,

I notice the following issue in the specification update (v31420) of the
au1550:

"System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale
data.

Description
-----------
System bus masters (USB host controller, PCI controller, MAC0, MAC1,
DDMA controller), when performing
coherent reads, may incorrectly receive stale data from memory instead
of valid modified data from the Au1
data cache. If the request for data arrives within a 3-clock window
prior to the cache line castout to memory,
the cache snoop response is incorrect and stale data is retrieved from
memory instead of the correct data from
the cache. The cache line castout then completes, and memory is updated.
Cache/memory data is not corrupted, but the specific bus read in not
valid.

Affected Step
-------------
AA

Workaround
----------
Do not enable cacheable master reads if the core modifies data in cache.

Status
------
Not Fixed"

Does somebody known if the linux kernel 2.6.10 integrates this
workaround ?

Thanks

Au1550 system bus masters issue

[David Sanchez]

Hi,

I notice the following issue in the specification update (v31420) of the
au1550:

"System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale
data.

Description
-----------
System bus masters (USB host controller, PCI controller, MAC0, MAC1,
DDMA controller), when performing
coherent reads, may incorrectly receive stale data from memory instead
of valid modified data from the Au1
data cache. If the request for data arrives within a 3-clock window
prior to the cache line castout to memory,
the cache snoop response is incorrect and stale data is retrieved from
memory instead of the correct data from
the cache. The cache line castout then completes, and memory is updated.
Cache/memory data is not corrupted, but the specific bus read in not
valid.

Affected Step
-------------
AA

Workaround
----------
Do not enable cacheable master reads if the core modifies data in cache.

Status
------
Not Fixed"

Does somebody known if the linux kernel 2.6.10 integrates this
workaround ?

Thanks

Re: Au1550 system bus masters issue

[Sergei Shtylylov]

Hello.

David Sanchez wrote:

> I notice the following issue in the specification update (v31420) of the
> au1550:
> 
> "System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale
> data.
> 
> Description
> -----------
> System bus masters (USB host controller, PCI controller, MAC0, MAC1,
> DDMA controller), when performing
> coherent reads, may incorrectly receive stale data from memory instead
> of valid modified data from the Au1
> data cache. If the request for data arrives within a 3-clock window
> prior to the cache line castout to memory,
> the cache snoop response is incorrect and stale data is retrieved from
> memory instead of the correct data from
> the cache. The cache line castout then completes, and memory is updated.
> Cache/memory data is not corrupted, but the specific bus read in not
> valid.
> 
> Affected Step
> -------------
> AA
> 
> Workaround
> ----------
> Do not enable cacheable master reads if the core modifies data in cache.
> 
> Status
> ------
> Not Fixed"
> 
> Does somebody known if the linux kernel 2.6.10 integrates this
> workaround ?

    Mainly as CONFIG_DMA_NONCOHERENT defined. USB OHCI and PCI still have
coherency enabled but as the cache hits prone to errata shouldn't happen due 
to the CONFIG_DMA_NONCOHERENT, it's probably not a problem (enabling coherency 
in Ethernet driver however makes the kernel non-bootable. USB host controller 
(and probably not only it, I'm too lazy to re-check ;-) is still prone to 
other errata on stepping AB though, see this thread:

http://www.linux-mips.org/archives/linux-mips/2005-11/msg00137.html

I'm gonna rework the patch and resubmit.

> Thanks

WBR, Sergei

Re: Au1550 system bus masters issue

[Sergei Shtylylov]

Hello.

Sergei Shtylylov wrote:

> coherency in Ethernet driver however makes the kernel non-bootable. USB 
> host controller (and probably not only it, I'm too lazy to re-check ;-) 
> is still prone to other errata on stepping AB though, see this thread:
> 
> http://www.linux-mips.org/archives/linux-mips/2005-11/msg00137.html
> 
> I'm gonna rework the patch and resubmit.

    Oops, I was talking of Au1500 step AB, Au1550 doesn't have CONFIG.OD bit 
errata...

WBR, Sergei

RE: Au1550 system bus masters issue

[David Sanchez]

Hi,

This question is for all the users of the AMD alchemy db1550:
What is the frequency you use for the triplet (CPU core / System bus / SDRAM bus)?

Since the version 2.25 of YAMON the freq is based on the rotary switch S4:
HEX Rotary Switch S4 (# = CPU_CORE / SYS_BUS / SDRAM_BUS  in MHz):

 0 = 192/ 96/ 96 , 1 = 336/168/168 , 2 = 396/198/ 99 , 3 = 396/198/198
 4 = 492/123/123 , 5 = 492/164/164 , 6 = 492/246/123

Thanks,

David SANCHEZ

-----Message d'origine-----
De : Sergei Shtylylov [mailto:sshtylyov@ru.mvista.com] 
Envoyé : lundi 5 décembre 2005 13:00
À : David Sanchez; Linux MIPS Development
Objet : Re: Au1550 system bus masters issue

Hello.

Sergei Shtylylov wrote:

> coherency in Ethernet driver however makes the kernel non-bootable. USB 
> host controller (and probably not only it, I'm too lazy to re-check ;-) 
> is still prone to other errata on stepping AB though, see this thread:
> 
> http://www.linux-mips.org/archives/linux-mips/2005-11/msg00137.html
> 
> I'm gonna rework the patch and resubmit.

    Oops, I was talking of Au1500 step AB, Au1550 doesn't have CONFIG.OD bit 
errata...

WBR, Sergei

RE: Au1550 system bus masters issue

[David Sanchez]

Hi,

This question is for all the users of the AMD alchemy db1550:
What is the frequency you use for the triplet (CPU core / System bus / SDRAM bus)?

Since the version 2.25 of YAMON the freq is based on the rotary switch S4:
HEX Rotary Switch S4 (# = CPU_CORE / SYS_BUS / SDRAM_BUS  in MHz):

 0 = 192/ 96/ 96 , 1 = 336/168/168 , 2 = 396/198/ 99 , 3 = 396/198/198
 4 = 492/123/123 , 5 = 492/164/164 , 6 = 492/246/123

Thanks,

David SANCHEZ

-----Message d'origine-----
De : Sergei Shtylylov [mailto:sshtylyov@ru.mvista.com] 
Envoyé : lundi 5 décembre 2005 13:00
À : David Sanchez; Linux MIPS Development
Objet : Re: Au1550 system bus masters issue

Hello.

Sergei Shtylylov wrote:

> coherency in Ethernet driver however makes the kernel non-bootable. USB 
> host controller (and probably not only it, I'm too lazy to re-check ;-) 
> is still prone to other errata on stepping AB though, see this thread:
> 
> http://www.linux-mips.org/archives/linux-mips/2005-11/msg00137.html
> 
> I'm gonna rework the patch and resubmit.

    Oops, I was talking of Au1500 step AB, Au1550 doesn't have CONFIG.OD bit 
errata...

WBR, Sergei