* Can I use this kind of performance counters to implement oProfile?
@ 2006-01-16 8:17 colin
2006-01-16 8:17 ` colin
2006-01-16 15:18 ` Fuxin Zhang
0 siblings, 2 replies; 3+ messages in thread
From: colin @ 2006-01-16 8:17 UTC (permalink / raw)
To: linux-mips
Hi all,
Our SOC has performance counters, and we would like to use oProfile on it.
After surveying the oProfile doc, I found that the model of our performance
counters donot seem to fit oProfile.
This is because oProfile uses the interrupts caused by overflow of, say,
cache miss count to estimate the probability of this event in every portion.
Our SOC doesn't emit interrupt when event count overflow. Therefore,
oProfile cannot be used to estimate cache miss event on our chip. Is that
right?
Regards,
Colin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Can I use this kind of performance counters to implement oProfile?
2006-01-16 8:17 Can I use this kind of performance counters to implement oProfile? colin
@ 2006-01-16 8:17 ` colin
2006-01-16 15:18 ` Fuxin Zhang
1 sibling, 0 replies; 3+ messages in thread
From: colin @ 2006-01-16 8:17 UTC (permalink / raw)
To: linux-mips
Hi all,
Our SOC has performance counters, and we would like to use oProfile on it.
After surveying the oProfile doc, I found that the model of our performance
counters donot seem to fit oProfile.
This is because oProfile uses the interrupts caused by overflow of, say,
cache miss count to estimate the probability of this event in every portion.
Our SOC doesn't emit interrupt when event count overflow. Therefore,
oProfile cannot be used to estimate cache miss event on our chip. Is that
right?
Regards,
Colin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Can I use this kind of performance counters to implement oProfile?
2006-01-16 8:17 Can I use this kind of performance counters to implement oProfile? colin
2006-01-16 8:17 ` colin
@ 2006-01-16 15:18 ` Fuxin Zhang
1 sibling, 0 replies; 3+ messages in thread
From: Fuxin Zhang @ 2006-01-16 15:18 UTC (permalink / raw)
To: colin; +Cc: linux-mips
You should be able to accumulate counters during process switching or a
timer routine, I managed to implement perfctr(another profiling
software) for godson-2 cpu, for both cases with/without interrupt
support. You can look at generic perfctr code.
colin 写道:
> Hi all,
> Our SOC has performance counters, and we would like to use oProfile on it.
> After surveying the oProfile doc, I found that the model of our performance
> counters donot seem to fit oProfile.
> This is because oProfile uses the interrupts caused by overflow of, say,
> cache miss count to estimate the probability of this event in every portion.
> Our SOC doesn't emit interrupt when event count overflow. Therefore,
> oProfile cannot be used to estimate cache miss event on our chip. Is that
> right?
>
> Regards,
> Colin
>
>
>
>
>
>
>
>
>
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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