Q: au1200 RCSn signal

Q: au1200 RCSn signal

[Changrui Zhang]

Hi!
I am learning ide driver based on AU1200 and the kernel is 2.6.11.The
CROSS_COMPILE I used is
gcc-3.3.5-glibc-2.3.2/mipsel-unknown-linux-gnu.When the ide driver used
RCS2 controller, it worked well.But when i change to use RCS1
controler,it didn't work.The both register MEM_STCFG and MEM_STTIME are
set same: MEM_STCFG 0xfe2401c6 MEM_STTIME 0x7f7ffc3f.I set the time to
max for testing.The RCS2 io_base is 0x18000000,the RCS1 io_base is
0x0c000000.So I set MEM_STADDR1 to 0x10c03f00.
I used the fallowing codes for testing:
while(1){
au_writeb(0xff,0xac000000);
}
I can't see any singal,such as CS,WE,DATA.But I added "udelay(4);" in
the while circle or just change au_writeb to au_readb(0xac000000),I
counld see all the signal is right(has signal).The testing codes as fallow:
while(1){
au_readb(0xac000000);
}
and
while(1){
udelay(4);
au_writeb(0xff,0xac000000)
}
In the testing,the IDE is not connected,as I just want to test the
signal is good or not.
Could someone tell me what wrong it is?Is there any different init
setting between RCS1 and RCS2?How I could make the RCS1 work?
I also come to the U-boot(U-boot1.1.4) to do the same testing after the
reset.The result is same.


reset:
#if 1
li t0, 0xb4001018 /*cs1 addr reg*/
li t1, 0x00
sw t1, 0(t0)

li t0, 0xb4001010/*cfg reg*/
li t1, 0xfe2401c6
sw t1, 0(t0)

li t0, 0xb4001014/*timer reg*/
li t1, 0x7f7ffc3f
sw t1, 0(t0)

li t0, 0xb4001018
li t1, 0x10c03f00
sw t1, 0(t0)

loop: li t0, 0xac000000
li t1, 0xff
sb t1, 0(t0)
b loop
#endif /*for test lzcx add*/
The test changing to CS2 control is good.

Thanks for your help in advance.


Mr.liang