[PATCH 0/2] Initial support for OCTEON

[PATCH 0/2] Initial support for OCTEON

[Tomaso Paoletti]

Hi all

This is a first (trivial) set of patches to pave the way for support of 
OCTEON processors in the kernel.

The set adds:
- Detection of OCTEON CPU variants in cpu_probe_cavium()
- Processor ID (PrID) constants
- Workaround (WAR) include file

Please consider for inclusion.
Thanks

   Tomaso Paoletti

Re: [PATCH 0/2] Initial support for OCTEON

[Ralf Baechle]

On Mon, Aug 18, 2008 at 02:17:14PM -0700, Tomaso Paoletti wrote:

> This is a first (trivial) set of patches to pave the way for support of  
> OCTEON processors in the kernel.
>
> The set adds:
> - Detection of OCTEON CPU variants in cpu_probe_cavium()
> - Processor ID (PrID) constants
> - Workaround (WAR) include file
>
> Please consider for inclusion.

So with the evil email monster having kept these mails without sharing them
with us...

I normally insist that there are users for new header files or functions
since otherwise the kernel janitors will remove them shortly ...

  Ralf

Re: [PATCH 0/2] Initial support for OCTEON

[Tomaso Paoletti]

Ralf Baechle wrote:
> On Mon, Aug 18, 2008 at 02:17:14PM -0700, Tomaso Paoletti wrote:
> 
>> This is a first (trivial) set of patches to pave the way for support of  
>> OCTEON processors in the kernel.
>>
>> The set adds:
>> - Detection of OCTEON CPU variants in cpu_probe_cavium()
>> - Processor ID (PrID) constants
>> - Workaround (WAR) include file
>>
>> Please consider for inclusion.
> 
> So with the evil email monster having kept these mails without sharing them
> with us...

We fed the 'evil email monster' with junk mail, and it let go of the 
original messages.
Quite an embarassment, sorry about that.

> I normally insist that there are users for new header files or functions
> since otherwise the kernel janitors will remove them shortly ...

Got it. I'm going to post users soon in a separate patchset, so that you 
can queue them in the reverse order (they are orthogonal), if that's ok 
with you.
Thanks

   Tomaso

[PATCH 1/2] OCTEON: Add processor-specific constants and detection of CPU variants

[Tomaso Paoletti]

Add constants for machine type, processor ID and MODULE_PROC_FAMILY for Octeon.
Add detection of all Cavium-specific ID strings for each processor variant.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
 arch/mips/kernel/cpu-probe.c |   35 +++++++++++++++++++++++++++++++++++
 include/asm-mips/bootinfo.h  |    5 +++++
 include/asm-mips/cpu.h       |   14 ++++++++++++++
 include/asm-mips/module.h    |    2 ++
 4 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae..3e104db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -160,6 +160,7 @@ static inline void check_wait(void)
 	case CPU_25KF:
 	case CPU_PR4450:
 	case CPU_BCM3302:
+	case CPU_CAVIUM_OCTEON:
 		cpu_wait = r4k_wait;
 		break;
 
@@ -821,6 +822,35 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
 	}
 }
 
+static inline void cpu_probe_cavium(struct cpuinfo_mips *c)
+{
+	switch (c->processor_id & 0xff00) {
+	case PRID_IMP_CAVIUM_CN38XX:
+	case PRID_IMP_CAVIUM_CN31XX:
+	case PRID_IMP_CAVIUM_CN30XX:
+	case PRID_IMP_CAVIUM_CN58XX:
+	case PRID_IMP_CAVIUM_CN56XX:
+	case PRID_IMP_CAVIUM_CN50XX:
+	case PRID_IMP_CAVIUM_CN52XX:
+		c->cputype = CPU_CAVIUM_OCTEON;
+		break;
+	default:
+		printk(KERN_INFO "Unknown Octeon chip!\n");
+		c->cputype = CPU_UNKNOWN;
+		break;
+	}
+
+	c->isa_level = MIPS_CPU_ISA_M64R2;
+	c->options = MIPS_CPU_TLB |     /* CPU has TLB */
+		     MIPS_CPU_4KEX |    /* "R4K" exception model */
+		     MIPS_CPU_COUNTER | /* Cycle count/compare */
+		     MIPS_CPU_WATCH |   /* watchpoint registers */
+		     MIPS_CPU_DIVEC |   /* dedicated int vector */
+		     MIPS_CPU_EJTAG |   /* EJTAG exception */
+		     MIPS_CPU_LLSC;     /* CPU has ll/sc instructions */
+	decode_config1(c);
+}
+
 const char *__cpu_name[NR_CPUS];
 
 /*
@@ -902,6 +932,8 @@ static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
 	case CPU_BCM4710:	name = "Broadcom BCM4710"; break;
 	case CPU_PR4450:	name = "Philips PR4450"; break;
 	case CPU_LOONGSON2:	name = "ICT Loongson-2"; break;
+	case CPU_CAVIUM_OCTEON:	name = "Cavium Octeon"; break;
+
 	default:
 		BUG();
 	}
@@ -941,6 +973,9 @@ __cpuinit void cpu_probe(void)
 	case PRID_COMP_NXP:
 		cpu_probe_nxp(c);
 		break;
+	case PRID_COMP_CAVIUM:
+		cpu_probe_cavium(c);
+		break;
 	default:
 		c->cputype = CPU_UNKNOWN;
 	}
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 610fe3a..ac34028 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -57,6 +57,11 @@
 #define	MACH_MIKROTIK_RB532	0	/* Mikrotik RouterBoard 532 	*/
 #define MACH_MIKROTIK_RB532A	1	/* Mikrotik RouterBoard 532A 	*/
 
+/*
+ * Valid machtype for group CAVIUM
+ */
+#define  MACH_CAVIUM_OCTEON	1	/* Cavium Octeon */
+
 #define CL_SIZE			COMMAND_LINE_SIZE
 
 extern char *system_type;
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 229a786..c018727 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -33,6 +33,7 @@
 #define PRID_COMP_TOSHIBA	0x070000
 #define PRID_COMP_LSI		0x080000
 #define PRID_COMP_LEXRA		0x0b0000
+#define PRID_COMP_CAVIUM	0x0d0000
 
 
 /*
@@ -114,6 +115,18 @@
 #define PRID_IMP_BCM3302	0x9000
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
+ */
+
+#define PRID_IMP_CAVIUM_CN38XX 0x0000
+#define PRID_IMP_CAVIUM_CN31XX 0x0100
+#define PRID_IMP_CAVIUM_CN30XX 0x0200
+#define PRID_IMP_CAVIUM_CN58XX 0x0300
+#define PRID_IMP_CAVIUM_CN56XX 0x0400
+#define PRID_IMP_CAVIUM_CN50XX 0x0600
+#define PRID_IMP_CAVIUM_CN52XX 0x0700
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -203,6 +216,7 @@ enum cpu_type_enum {
 	 * MIPS64 class processors
 	 */
 	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+	CPU_CAVIUM_OCTEON,
 
 	CPU_LAST
 };
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index de6d09e..7b24183 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -114,6 +114,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_CAVIUM_OCTEON
+#define MODULE_PROC_FAMILY "OCTEON "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
-- 
1.5.3.2

Re: [PATCH 1/2] OCTEON: Add processor-specific constants and detection of CPU variants

[Thomas Bogendoerfer]

On Wed, Aug 20, 2008 at 01:20:05PM -0700, Tomaso Paoletti wrote:
> --- a/include/asm-mips/bootinfo.h
> +++ b/include/asm-mips/bootinfo.h
> @@ -57,6 +57,11 @@
>  #define	MACH_MIKROTIK_RB532	0	/* Mikrotik RouterBoard 532 	*/
>  #define MACH_MIKROTIK_RB532A	1	/* Mikrotik RouterBoard 532A 	*/
>  
> +/*
> + * Valid machtype for group CAVIUM
> + */
> +#define  MACH_CAVIUM_OCTEON	1	/* Cavium Octeon */
> +

no new machtypes please.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH 1/2] OCTEON: Add processor-specific constants and detection of CPU variants

[Tomaso Paoletti]

Hi Thomas

Thomas Bogendoerfer wrote:
> On Wed, Aug 20, 2008 at 01:20:05PM -0700, Tomaso Paoletti wrote:
>> --- a/include/asm-mips/bootinfo.h
>> +++ b/include/asm-mips/bootinfo.h
>> @@ -57,6 +57,11 @@
>>  #define	MACH_MIKROTIK_RB532	0	/* Mikrotik RouterBoard 532 	*/
>>  #define MACH_MIKROTIK_RB532A	1	/* Mikrotik RouterBoard 532A 	*/
>>  
>> +/*
>> + * Valid machtype for group CAVIUM
>> + */
>> +#define  MACH_CAVIUM_OCTEON	1	/* Cavium Octeon */
>> +
> 
> no new machtypes please.

Thanks, I've corrected that.
I'm waiting to see if there's more feedback, and will resend the patch 
by this afternoon (PST).

   Tomaso

[PATCH 2/2] OCTEON: Add workaround file

[Tomaso Paoletti]

Add OCTEON specific version of the workarounds file.
None of these apply to OCTEON, but the file is required.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
 include/asm-mips/mach-cavium-octeon/war.h |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-mips/mach-cavium-octeon/war.h

diff --git a/include/asm-mips/mach-cavium-octeon/war.h b/include/asm-mips/mach-cavium-octeon/war.h
new file mode 100644
index 0000000..c4712d7
--- /dev/null
+++ b/include/asm-mips/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
+ */
+#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
-- 
1.5.3.2

Re: [PATCH 2/2] OCTEON: Add workaround file

[Ralf Baechle]

On Wed, Aug 20, 2008 at 01:20:25PM -0700, Tomaso Paoletti wrote:

> Add OCTEON specific version of the workarounds file.
> None of these apply to OCTEON, but the file is required.

Yes - intentionally.  I want to force people having to think about if they
need any of the workaround enabled because the bugs from not having a
necessary workaround enabled could be painfully subtle.

  Ralf

Re: [PATCH 2/2] OCTEON: Add workaround file

[Tomaso Paoletti]

Ralf Baechle wrote:
> On Wed, Aug 20, 2008 at 01:20:25PM -0700, Tomaso Paoletti wrote:
> 
>> Add OCTEON specific version of the workarounds file.
>> None of these apply to OCTEON, but the file is required.
> 
> Yes - intentionally.  I want to force people having to think about if they
> need any of the workaround enabled because the bugs from not having a
> necessary workaround enabled could be painfully subtle.

I've modified the patch comment to confirm that we verified the 
applicability of all defines.
Thanks

   Tomaso

[PATCH v2 1/2] OCTEON: Add processor-specific constants and detection of CPU variants

[Tomaso Paoletti]

Add:
- Processor ID constants specific to Cavium;
- MODULE_PROC_FAMILY string for OCTEON;
- Probe function to detect all processor variants;
- Proper cpu_to_name() case.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
 arch/mips/kernel/cpu-probe.c |   35 +++++++++++++++++++++++++++++++++++
 include/asm-mips/cpu.h       |   14 ++++++++++++++
 include/asm-mips/module.h    |    2 ++
 3 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae..3e104db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -160,6 +160,7 @@ static inline void check_wait(void)
 	case CPU_25KF:
 	case CPU_PR4450:
 	case CPU_BCM3302:
+	case CPU_CAVIUM_OCTEON:
 		cpu_wait = r4k_wait;
 		break;
 
@@ -821,6 +822,35 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
 	}
 }
 
+static inline void cpu_probe_cavium(struct cpuinfo_mips *c)
+{
+	switch (c->processor_id & 0xff00) {
+	case PRID_IMP_CAVIUM_CN38XX:
+	case PRID_IMP_CAVIUM_CN31XX:
+	case PRID_IMP_CAVIUM_CN30XX:
+	case PRID_IMP_CAVIUM_CN58XX:
+	case PRID_IMP_CAVIUM_CN56XX:
+	case PRID_IMP_CAVIUM_CN50XX:
+	case PRID_IMP_CAVIUM_CN52XX:
+		c->cputype = CPU_CAVIUM_OCTEON;
+		break;
+	default:
+		printk(KERN_INFO "Unknown Octeon chip!\n");
+		c->cputype = CPU_UNKNOWN;
+		break;
+	}
+
+	c->isa_level = MIPS_CPU_ISA_M64R2;
+	c->options = MIPS_CPU_TLB |     /* CPU has TLB */
+		     MIPS_CPU_4KEX |    /* "R4K" exception model */
+		     MIPS_CPU_COUNTER | /* Cycle count/compare */
+		     MIPS_CPU_WATCH |   /* watchpoint registers */
+		     MIPS_CPU_DIVEC |   /* dedicated int vector */
+		     MIPS_CPU_EJTAG |   /* EJTAG exception */
+		     MIPS_CPU_LLSC;     /* CPU has ll/sc instructions */
+	decode_config1(c);
+}
+
 const char *__cpu_name[NR_CPUS];
 
 /*
@@ -902,6 +932,8 @@ static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
 	case CPU_BCM4710:	name = "Broadcom BCM4710"; break;
 	case CPU_PR4450:	name = "Philips PR4450"; break;
 	case CPU_LOONGSON2:	name = "ICT Loongson-2"; break;
+	case CPU_CAVIUM_OCTEON:	name = "Cavium Octeon"; break;
+
 	default:
 		BUG();
 	}
@@ -941,6 +973,9 @@ __cpuinit void cpu_probe(void)
 	case PRID_COMP_NXP:
 		cpu_probe_nxp(c);
 		break;
+	case PRID_COMP_CAVIUM:
+		cpu_probe_cavium(c);
+		break;
 	default:
 		c->cputype = CPU_UNKNOWN;
 	}
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 229a786..c018727 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -33,6 +33,7 @@
 #define PRID_COMP_TOSHIBA	0x070000
 #define PRID_COMP_LSI		0x080000
 #define PRID_COMP_LEXRA		0x0b0000
+#define PRID_COMP_CAVIUM	0x0d0000
 
 
 /*
@@ -114,6 +115,18 @@
 #define PRID_IMP_BCM3302	0x9000
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
+ */
+
+#define PRID_IMP_CAVIUM_CN38XX 0x0000
+#define PRID_IMP_CAVIUM_CN31XX 0x0100
+#define PRID_IMP_CAVIUM_CN30XX 0x0200
+#define PRID_IMP_CAVIUM_CN58XX 0x0300
+#define PRID_IMP_CAVIUM_CN56XX 0x0400
+#define PRID_IMP_CAVIUM_CN50XX 0x0600
+#define PRID_IMP_CAVIUM_CN52XX 0x0700
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -203,6 +216,7 @@ enum cpu_type_enum {
 	 * MIPS64 class processors
 	 */
 	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+	CPU_CAVIUM_OCTEON,
 
 	CPU_LAST
 };
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index de6d09e..7b24183 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -114,6 +114,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_CAVIUM_OCTEON
+#define MODULE_PROC_FAMILY "OCTEON "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
-- 
1.5.3.2

[PATCH v2 2/2] OCTEON: Add workaround file

[Tomaso Paoletti]

Add OCTEON-specific version of the workarounds file.
Verified that none of the existing defines applies to the processor.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
 include/asm-mips/mach-cavium-octeon/war.h |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-mips/mach-cavium-octeon/war.h

diff --git a/include/asm-mips/mach-cavium-octeon/war.h b/include/asm-mips/mach-cavium-octeon/war.h
new file mode 100644
index 0000000..c4712d7
--- /dev/null
+++ b/include/asm-mips/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
+ */
+#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
-- 
1.5.3.2