Re: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform.

[Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>]

Hello,

On 4/8/2012 1:48 AM, Steven J. Hill wrote:
> diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
> new file mode 100644
> index 0000000..7f3e3f9
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
> @@ -0,0 +1,72 @@
[...]
> +/*
> + * CPU feature overrides for MIPS boards
> + */
> +#ifdef CONFIG_CPU_MIPS32
> +#define cpu_has_tlb		1
> +#define cpu_has_4kex		1
> +#define cpu_has_4k_cache	1
> +/* #define cpu_has_fpu		? */
> +/* #define cpu_has_32fpr	? */
> +#define cpu_has_counter		1
> +/* #define cpu_has_watch	? */
> +#define cpu_has_divec		1
> +#define cpu_has_vce		0
> +/* #define cpu_has_cache_cdex_p	? */
> +/* #define cpu_has_cache_cdex_s	? */
> +/* #define cpu_has_prefetch	? */
> +#define cpu_has_mcheck		1
> +/* #define cpu_has_ejtag	? */
> +#ifdef CONFIG_CPU_HAS_LLSC
> +#define cpu_has_llsc		1
> +#else
> +#define cpu_has_llsc		0
> +#endif

This Ralf's commit maybe be still valid for sead3 board?

http://git.kernel.org/linus/b8d6f78cd058e34ec706f7cb353fdb2eb743c050
MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC

> +/* #define cpu_has_vtag_icache	? */
> +/* #define cpu_has_dc_aliases	? */
> +/* #define cpu_has_ic_fills_f_dc ? */
> +#define cpu_has_nofpuex		0
> +/* #define cpu_has_64bits	? */
> +/* #define cpu_has_64bit_zero_reg ? */
> +/* #define cpu_has_inclusive_pcaches ? */
> +#define cpu_icache_snoops_remote_store 1
> +#endif

Also you might be interested in fls/ffs optimization using CLO/CLZ
instruction, that will be used in irq_ffs() at plat_irq_dispatch:

https://patchwork.linux-mips.org/patch/1453/
MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platforms

Some discussions on this is found at:
http://www.linux-mips.org/archives/linux-mips/2010-07/msg00000.html

> diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
> new file mode 100644
> index 0000000..4cd569e
> --- /dev/null
> +++ b/arch/mips/mti-sead3/sead3-int.c
> @@ -0,0 +1,146 @@
[...]
> +/*
> + * Version of ffs that only looks at bits 8..15
> + */
> +static inline unsigned int irq_ffs(unsigned int pending)
> +{
> +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
> +	return fls(pending) - CAUSEB_IP - 1;
> +#else
> +	unsigned int a0 = 7;
> +	unsigned int t0;
> +
> +	t0 = pending & 0xf000;
> +	t0 = t0 < 1;
> +	t0 = t0 << 2;
> +	a0 = a0 - t0;
> +	pending = pending << t0;
> +
> +	t0 = pending & 0xc000;
> +	t0 = t0 < 1;
> +	t0 = t0 << 1;
> +	a0 = a0 - t0;
> +	pending = pending << t0;
> +
> +	t0 = pending & 0x8000;
> +	t0 = t0 < 1;
> +	/* t0 = t0 << 2; */
> +	a0 = a0 - t0;
> +	/* pending = pending << t0; */
> +
> +	return a0;
> +#endif
> +}
> +
> +asmlinkage void plat_irq_dispatch(void)
> +{
> +	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
> +	int irq;
> +
> +	irq = irq_ffs(pending);
> +
> +	if (irq >= 0)
> +		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
> +	else
> +		spurious_interrupt();
> +}

-- 
Shinya Kuribayashi
Renesas Electronics