From: John Crispin <john@phrozen.org>
To: linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: add irqdomain support for the CPU IRQ controller
Date: Tue, 29 Jan 2013 19:32:43 +0100 [thread overview]
Message-ID: <510815CB.7030100@phrozen.org> (raw)
In-Reply-To: <51080992.6030905@gmail.com>
> Is it necessary to use the word 'intc'? What does that mean? Perhaps
> "mti,cpu-interrupt-controller"?
>
the name is only a detail and if you prefer said name i have no prolem
with that.
>> Please use this as an actual device tree documentation binding.
>
> Yes, bindings should be documented in
> Documentation/devicetree/bindings/mips
Sure i will repost in a bit with a binding document
> Just to satisfy my curiosity, Which drivers are using (or will be using)
> these mapping facilities? The timer and performance counters already
> work, so it isn't needed for them. What will use this.
we updated the ralink series i posted a few days ago to make use of this
patch.
the SoC has its own irq controller behind STATUSF_IP2.
STATUSF_IP5 is wired to ethernet and STATUSF_IP6 is wired to wifi
i think on some socs from ralink the pci is wired to STATUSF_IP3
to be able to nicely represent this in a devicetree we need an entry for
the mips cpu interrupt controller.
as the patch no exists I am considering to update the lantiq code to
make use of it. Also the patch originates from gabors ath79 devicetree
series, which also makes use of it.
John
prev parent reply other threads:[~2013-01-29 18:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-28 21:59 [PATCH] MIPS: add irqdomain support for the CPU IRQ controller John Crispin
2013-01-28 22:12 ` Florian Fainelli
2013-01-29 17:40 ` David Daney
2013-01-29 18:32 ` John Crispin [this message]
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