[PATCH 1/4] MIPS: lantiq: adds 4dword burst length for dma

[PATCH 1/4] MIPS: lantiq: adds 4dword burst length for dma

[John Crispin]

Comparing the upstream code with the Lantiq UGW kernel we see that burst length
should be set to 4 bytes.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/dma.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 08f7ebd..ccf1451 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -48,6 +48,7 @@
 #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
 #define DMA_POLL		BIT(31)		/* turn on channel polling */
 #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
+#define DMA_4W_BURST		BIT(2)		/* 4 word burst length */
 #define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
 #define DMA_MAX_CHANNEL		20		/* the soc has 20 channels */
 #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
@@ -196,7 +197,8 @@ ltq_dma_init_port(int p)
 		 * Tell the DMA engine to swap the endianness of data frames and
 		 * drop packets if the channel arbitration fails.
 		 */
-		ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
+		ltq_dma_w32_mask(0, (DMA_4W_BURST << 4) | (DMA_4W_BURST << 2) |
+			DMA_ETOP_ENDIANNESS | DMA_PDEN,
 			LTQ_DMA_PCTRL);
 		break;
 
-- 
1.7.10.4

[PATCH 2/4] MIPS: lantiq: adds minimal dcdc driver

[John Crispin]

This driver so far only reads the core voltage.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/Makefile |    2 +-
 arch/mips/lantiq/xway/dcdc.c   |   75 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/lantiq/xway/dcdc.c

diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 7a13660..087497d 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 
 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
new file mode 100644
index 0000000..6361c30
--- /dev/null
+++ b/arch/mips/lantiq/xway/dcdc.c
@@ -0,0 +1,75 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2010 Sameer Ahmad, Lantiq GmbH
+ */
+
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+
+#include <lantiq_soc.h>
+
+/* Bias and regulator Setup Register */
+#define DCDC_BIAS_VREG0	0xa
+/* Bias and regulator Setup Register */
+#define DCDC_BIAS_VREG1	0xb
+
+#define dcdc_w8(x, y)	ltq_w8((x), dcdc_membase + (y))
+#define dcdc_r8(x)	ltq_r8(dcdc_membase + (x))
+
+static void __iomem *dcdc_membase;
+
+static int dcdc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Failed to get resource\n");
+		return -ENOMEM;
+	}
+
+	/* remap dcdc register range */
+	dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);
+	if (!dcdc_membase) {
+		dev_err(&pdev->dev, "Failed to remap resource\n");
+		return -ENOMEM;
+	}
+
+	dev_info(&pdev->dev, "Core Voltage : %d mV\n",
+		dcdc_r8(DCDC_BIAS_VREG1) * 8);
+
+	return 0;
+}
+
+static const struct of_device_id dcdc_match[] = {
+	{ .compatible = "lantiq,dcdc-xrx200" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dcdc_match);
+
+static struct platform_driver dcdc_driver = {
+	.probe = dcdc_probe,
+	.driver = {
+		.name = "dcdc-xrx200",
+		.owner = THIS_MODULE,
+		.of_match_table = dcdc_match,
+	},
+};
+
+int __init dcdc_init(void)
+{
+	int ret = platform_driver_register(&dcdc_driver);
+
+	if (ret)
+		pr_info("dcdc: Error registering platform driver\n");
+	return ret;
+}
+
+arch_initcall(dcdc_init);
-- 
1.7.10.4

Re: [PATCH 2/4] MIPS: lantiq: adds minimal dcdc driver

[Sergei Shtylyov]

Hello.

On 08-08-2013 13:07, John Crispin wrote:

> This driver so far only reads the core voltage.

> Signed-off-by: John Crispin <blogic@openwrt.org>
[...]

> diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
> new file mode 100644
> index 0000000..6361c30
> --- /dev/null
> +++ b/arch/mips/lantiq/xway/dcdc.c
> @@ -0,0 +1,75 @@
[...]
> +static int dcdc_probe(struct platform_device *pdev)
> +{
> +	struct resource *res;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "Failed to get resource\n");
> +		return -ENOMEM;
> +	}

    You do not need to check this with devm_request_and_ioremap() or
devm_ioremap_resource().

> +
> +	/* remap dcdc register range */
> +	dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);

    Use devm_ioremap_resource().

> +	if (!dcdc_membase) {
> +		dev_err(&pdev->dev, "Failed to remap resource\n");

    Error messages are already printed by devm_request_and_ioremap() 
ordevm_ioremap_resource().

> +		return -ENOMEM;

    -EADDRNOTAVAIL is the right code for devm_request_and_ioremap().

WBR, Sergei

Re: [PATCH 2/4] MIPS: lantiq: adds minimal dcdc driver

[Florian Fainelli]

2013/8/8 Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>:
> Hello.
>
>
> On 08-08-2013 13:07, John Crispin wrote:
>
>> This driver so far only reads the core voltage.
>
>
>> Signed-off-by: John Crispin <blogic@openwrt.org>
>
> [...]
>
>
>> diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
>> new file mode 100644
>> index 0000000..6361c30
>> --- /dev/null
>> +++ b/arch/mips/lantiq/xway/dcdc.c
>> @@ -0,0 +1,75 @@
>
> [...]
>
>> +static int dcdc_probe(struct platform_device *pdev)
>> +{
>> +       struct resource *res;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       if (!res) {
>> +               dev_err(&pdev->dev, "Failed to get resource\n");
>> +               return -ENOMEM;
>> +       }
>
>
>    You do not need to check this with devm_request_and_ioremap() or
> devm_ioremap_resource().
>
>
>> +
>> +       /* remap dcdc register range */
>> +       dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);
>
>
>    Use devm_ioremap_resource().
>
>
>> +       if (!dcdc_membase) {
>> +               dev_err(&pdev->dev, "Failed to remap resource\n");
>
>
>    Error messages are already printed by devm_request_and_ioremap()
> ordevm_ioremap_resource().
>
>> +               return -ENOMEM;
>
>
>    -EADDRNOTAVAIL is the right code for devm_request_and_ioremap().

This is the first time that I read this, lib/devres.c internal returns
-ENOMEM when an ioremap() call fails (see devm_ioremap_resource),
-EADDRNOTAVAIL really is for networking matter, this is not.
-- 
Florian

Re: [PATCH 2/4] MIPS: lantiq: adds minimal dcdc driver

[Lars-Peter Clausen]

On 08/08/2013 01:17 PM, Florian Fainelli wrote:
> 2013/8/8 Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>:
>> Hello.
>>
>>
>> On 08-08-2013 13:07, John Crispin wrote:
>>
>>> This driver so far only reads the core voltage.
>>
>>
>>> Signed-off-by: John Crispin <blogic@openwrt.org>
>>
>> [...]
>>
>>
>>> diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
>>> new file mode 100644
>>> index 0000000..6361c30
>>> --- /dev/null
>>> +++ b/arch/mips/lantiq/xway/dcdc.c
>>> @@ -0,0 +1,75 @@
>>
>> [...]
>>
>>> +static int dcdc_probe(struct platform_device *pdev)
>>> +{
>>> +       struct resource *res;
>>> +
>>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +       if (!res) {
>>> +               dev_err(&pdev->dev, "Failed to get resource\n");
>>> +               return -ENOMEM;
>>> +       }
>>
>>
>>     You do not need to check this with devm_request_and_ioremap() or
>> devm_ioremap_resource().
>>
>>
>>> +
>>> +       /* remap dcdc register range */
>>> +       dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);
>>
>>
>>     Use devm_ioremap_resource().
>>
>>
>>> +       if (!dcdc_membase) {
>>> +               dev_err(&pdev->dev, "Failed to remap resource\n");
>>
>>
>>     Error messages are already printed by devm_request_and_ioremap()
>> ordevm_ioremap_resource().
>>
>>> +               return -ENOMEM;
>>
>>
>>     -EADDRNOTAVAIL is the right code for devm_request_and_ioremap().
>
> This is the first time that I read this, lib/devres.c internal returns
> -ENOMEM when an ioremap() call fails (see devm_ioremap_resource),
> -EADDRNOTAVAIL really is for networking matter, this is not.
>

You shouldn't need worry about the return code in this case anyway. This is the 
correct pattern for situations like this:

res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
	return PTR_ERR(base);

- Lars

Re: [PATCH 2/4] MIPS: lantiq: adds minimal dcdc driver

[Sergei Shtylyov]

Hello.

On 08-08-2013 15:17, Florian Fainelli wrote:

>>> This driver so far only reads the core voltage.

>>> Signed-off-by: John Crispin <blogic@openwrt.org>

>> [...]

>>> diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
>>> new file mode 100644
>>> index 0000000..6361c30
>>> --- /dev/null
>>> +++ b/arch/mips/lantiq/xway/dcdc.c
>>> @@ -0,0 +1,75 @@

>> [...]

>>> +
>>> +       /* remap dcdc register range */
>>> +       dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);

>>     Use devm_ioremap_resource().

>>> +       if (!dcdc_membase) {
>>> +               dev_err(&pdev->dev, "Failed to remap resource\n");

>>     Error messages are already printed by devm_request_and_ioremap()
>> ordevm_ioremap_resource().

>>> +               return -ENOMEM;

>>     -EADDRNOTAVAIL is the right code for devm_request_and_ioremap().

> This is the first time that I read this, lib/devres.c internal returns
> -ENOMEM when an ioremap() call fails

    What if the other call fails?

> (see devm_ioremap_resource),
> -EADDRNOTAVAIL really is for networking matter, this is not.

    Just see the comment accompanying devm_request_and_ioremap().

WBR, Sergei

[PATCH 3/4] MIPS: lantiq: falcon: add cpu-feature-override.h

[John Crispin]

From: Thomas Langer <thomas.langer@lantiq.com>

Add cpu-feature-override.h for the GPON SoC

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
---
 .../asm/mach-lantiq/falcon/cpu-feature-overrides.h |   58 ++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
new file mode 100644
index 0000000..096a100
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -0,0 +1,58 @@
+/*
+ *  Lantiq FALCON specific CPU feature overrides
+ *
+ *  Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *	Copyright (C) 2003, 2004 Ralf Baechle
+ *	Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_3k_cache	0
+#define cpu_has_4k_cache	1
+#define cpu_has_tx39_cache	0
+#define cpu_has_sb1_cache	0
+#define cpu_has_fpu		0
+#define cpu_has_32fpr		0
+#define cpu_has_counter		1
+#define cpu_has_watch		1
+#define cpu_has_divec		1
+
+#define cpu_has_prefetch	1
+#define cpu_has_ejtag		1
+#define cpu_has_llsc		1
+
+#define cpu_has_mips16		1
+#define cpu_has_mdmx		0
+#define cpu_has_mips3d		0
+#define cpu_has_smartmips	0
+
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	0
+#define cpu_has_mips64r2	0
+
+#define cpu_has_dsp		1
+#define cpu_has_mipsmt		1
+
+#define cpu_has_vint		1
+#define cpu_has_veic		1
+
+#define cpu_has_64bits		0
+#define cpu_has_64bit_zero_reg	0
+#define cpu_has_64bit_gp_regs	0
+#define cpu_has_64bit_addresses	0
+
+#define cpu_dcache_line_size()	32
+#define cpu_icache_line_size()	32
+
+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
-- 
1.7.10.4

[PATCH 4/4] MIPS: lantiq: falcon: fix asc clock definition

[John Crispin]

From: Thomas Langer <thomas.langer@lantiq.com>

The clocks of the serial ports were not setup properly.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/falcon/sysctrl.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index ff4894a..8f1866d 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -48,6 +48,7 @@
 #define CPU0CC_CPUDIV		0x0001
 
 /* Activation Status Register */
+#define ACTS_ASC0_ACT	0x00001000
 #define ACTS_ASC1_ACT	0x00000800
 #define ACTS_I2C_ACT	0x00004000
 #define ACTS_P0		0x00010000
@@ -108,6 +109,7 @@ static void sysctl_deactivate(struct clk *clk)
 static int sysctl_clken(struct clk *clk)
 {
 	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
+	sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
 	sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
 	return 0;
 }
@@ -256,6 +258,7 @@ void __init ltq_soc_init(void)
 	clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
 	clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
 	clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
-	clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
+	clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
+	clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
 	clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
 }
-- 
1.7.10.4

Re: [PATCH 1/4] MIPS: lantiq: adds 4dword burst length for dma

[Thomas Bogendoerfer]

On Thu, Aug 08, 2013 at 11:07:23AM +0200, John Crispin wrote:
> Comparing the upstream code with the Lantiq UGW kernel we see that burst length
> should be set to 4 bytes.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/lantiq/xway/dma.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
> index 08f7ebd..ccf1451 100644
> --- a/arch/mips/lantiq/xway/dma.c
> +++ b/arch/mips/lantiq/xway/dma.c
> @@ -48,6 +48,7 @@
>  #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
>  #define DMA_POLL		BIT(31)		/* turn on channel polling */
>  #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
> +#define DMA_4W_BURST		BIT(2)		/* 4 word burst length */
>  #define DMA_2W_BURST		BIT(1)		/* 2 word burst length */

that's wrong, it's not BIT(x), but x itself.

1 means 2 word burst
2 means 4 word burst
3 means 8 word burst

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]