From: Paul Burton <paul.burton@imgtec.com>
To: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>,
<linux-mips@linux-mips.org>, <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: Fix errata for some 1074K cores.
Date: Thu, 12 Sep 2013 10:39:18 +0100 [thread overview]
Message-ID: <52318BC6.7030903@imgtec.com> (raw)
In-Reply-To: <1378929708-7253-1-git-send-email-Steven.Hill@imgtec.com>
Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...
Paul
On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/c-r4k.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
> * aliases. In this case it is better to treat the cache as always
> * having aliases.
> */
> - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> - c->dcache.flags |= MIPS_CACHE_VTAG;
> - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> + if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
> c->dcache.flags |= MIPS_CACHE_VTAG;
> write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> }
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com>
To: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>,
linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH] MIPS: Fix errata for some 1074K cores.
Date: Thu, 12 Sep 2013 10:39:18 +0100 [thread overview]
Message-ID: <52318BC6.7030903@imgtec.com> (raw)
Message-ID: <20130912093918.0PeL1WSaO-1klCa1LVMUdKj-MPllxBJ8T9gPgol1sPw@z> (raw)
In-Reply-To: <1378929708-7253-1-git-send-email-Steven.Hill@imgtec.com>
Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...
Paul
On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/c-r4k.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
> * aliases. In this case it is better to treat the cache as always
> * having aliases.
> */
> - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> - c->dcache.flags |= MIPS_CACHE_VTAG;
> - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> + if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
> c->dcache.flags |= MIPS_CACHE_VTAG;
> write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> }
next prev parent reply other threads:[~2013-09-12 9:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-11 20:01 [PATCH] MIPS: Fix errata for some 1074K cores Steven J. Hill
2013-09-12 9:39 ` Paul Burton [this message]
2013-09-12 9:39 ` Paul Burton
2013-09-12 14:57 ` Leonid Yegoshin
2013-09-12 15:05 ` Florian Fainelli
2013-09-12 15:12 ` Leonid Yegoshin
2013-09-12 15:12 ` Paul Burton
2013-09-12 15:30 ` Leonid Yegoshin
2013-09-12 15:50 ` Florian Fainelli
2013-09-12 16:02 ` Steven J. Hill
2013-09-12 16:02 ` Steven J. Hill
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52318BC6.7030903@imgtec.com \
--to=paul.burton@imgtec.com \
--cc=Leonid.Yegoshin@imgtec.com \
--cc=Steven.Hill@imgtec.com \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox