From: "Steven J. Hill" <Steven.Hill@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching.
Date: Tue, 21 Jan 2014 14:58:44 -0600 [thread overview]
Message-ID: <52DEDF84.1000006@imgtec.com> (raw)
In-Reply-To: <20140121204938.GW14169@linux-mips.org>
On 01/21/2014 02:49 PM, Ralf Baechle wrote:
> On Tue, Jan 21, 2014 at 10:18:42AM -0600, Steven J. Hill wrote:
>
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>>
>> Use the PREF instruction to optimize partial checksum operations.
>
> Prefetch operations may cause obscure bus error exceptions on some systems
> such as Malta, for example, when prefetching beyond the end of memory.
> It may also mean memory regions that are just undergoing a DMA transfer
> are being brought back into cache.
>
> This pretty much means that pref is only safe to use on cache-coherent
> systems.
>
So, could we have:
#ifdef CONFIG_DMA_NONCOHERENT
#undef CONFIG_CPU_HAS_PREFETCH
#endif
#define PREFSIZE (1 << MIPS_L1_CACHE_SHIFT)
and then use the PREFSIZE value instead of the hardcoded value of 32?
Steve
WARNING: multiple messages have this Message-ID (diff)
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching.
Date: Tue, 21 Jan 2014 14:58:44 -0600 [thread overview]
Message-ID: <52DEDF84.1000006@imgtec.com> (raw)
Message-ID: <20140121205844.Cndx8plbkUY-RP7mfzh241wv8KzFp4UMb0OEV_jMy8A@z> (raw)
In-Reply-To: <20140121204938.GW14169@linux-mips.org>
On 01/21/2014 02:49 PM, Ralf Baechle wrote:
> On Tue, Jan 21, 2014 at 10:18:42AM -0600, Steven J. Hill wrote:
>
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>>
>> Use the PREF instruction to optimize partial checksum operations.
>
> Prefetch operations may cause obscure bus error exceptions on some systems
> such as Malta, for example, when prefetching beyond the end of memory.
> It may also mean memory regions that are just undergoing a DMA transfer
> are being brought back into cache.
>
> This pretty much means that pref is only safe to use on cache-coherent
> systems.
>
So, could we have:
#ifdef CONFIG_DMA_NONCOHERENT
#undef CONFIG_CPU_HAS_PREFETCH
#endif
#define PREFSIZE (1 << MIPS_L1_CACHE_SHIFT)
and then use the PREFSIZE value instead of the hardcoded value of 32?
Steve
next prev parent reply other threads:[~2014-01-21 20:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 16:18 [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching Steven J. Hill
2014-01-21 17:37 ` Florian Fainelli
2014-01-21 18:25 ` David Daney
2014-01-21 20:16 ` Steven J. Hill
2014-01-21 20:25 ` Florian Fainelli
2014-01-21 20:49 ` Ralf Baechle
2014-01-21 20:58 ` Steven J. Hill [this message]
2014-01-21 20:58 ` Steven J. Hill
2014-01-21 21:03 ` David Daney
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