Re: [PATCH 06/15] MIPS: Add minimal support for OCTEON3 to c-r4k.c

[James Hogan <james.hogan@imgtec.com>]

On 20/05/14 15:47, Andreas Herrmann wrote:
> From: David Daney <david.daney@cavium.com>
> 
> These are needed to boot a generic mips64r2 kernel on OCTEONIII.
> 
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
> ---
>  arch/mips/include/asm/r4kcache.h |    2 ++
>  arch/mips/mm/c-r4k.c             |   32 ++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 1c74a6a..789ede9 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c

> @@ -1094,6 +1110,21 @@ static void probe_pcache(void)
>  		c->dcache.waybit = 0;
>  		break;
>  
> +	case CPU_CAVIUM_OCTEON3:
> +		/* For now lie about the number of ways. */

Is this to work around the finite length of way_string[]?

Can we fix that to be more dynamic instead? (admittedly special casing
"direct mapped" looks like a bit of a pain).

Cheers
James

> +		c->icache.linesz = 128;
> +		c->icache.sets = 16;
> +		c->icache.ways = 8;
> +		c->icache.flags |= MIPS_CACHE_VTAG;
> +		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
> +
> +		c->dcache.linesz = 128;
> +		c->dcache.ways = 8;
> +		c->dcache.sets = 8;
> +		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
> +		c->options |= MIPS_CPU_PREFETCH;
> +		break;
> +