From: "Steven J. Hill" <Steven.Hill@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: <linux-mips@linux-mips.org>, <ralf@linux-mips.org>
Subject: Re: [PATCH V7 1/3] MIPS: Rearrange PTE bits into fixed positions.
Date: Thu, 26 Feb 2015 21:38:33 -0600 [thread overview]
Message-ID: <54EFE6B9.1050109@imgtec.com> (raw)
In-Reply-To: <54EFBF9D.4020004@gmail.com>
On 02/26/2015 06:51 PM, David Daney wrote:
>
> That's not really what I meant in my previous response on the subject.
> When I said:
>
> Why not just use RI for everything, instead of taking up two bits
> to represent a single binary concept?
>
> For the case where there is no RI hardware active, it is a purely
> software bit and you can easily invert the meaning and just have a
> _PAGE_NO_READ bit.
>
> I envisioned something like:
>
> 64-bit, all revisions: CCC D V G RI XI [S H] M A W P
> 32-bit, all revisions: CCC D V G RI XI M A W P
>
Which is what I implemented. I now only use one bit that functions
either as _PAGE_READ or _PAGE_READ_ONLY depending on the RI/XI
functionality present. Did you bother to read the code and understand
it, or just look at the commit message?
Steve
WARNING: multiple messages have this Message-ID (diff)
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH V7 1/3] MIPS: Rearrange PTE bits into fixed positions.
Date: Thu, 26 Feb 2015 21:38:33 -0600 [thread overview]
Message-ID: <54EFE6B9.1050109@imgtec.com> (raw)
Message-ID: <20150227033833.eW9jUI3HDQxM4gftkYJlaUdphrUFjrZoVLzKpuEcbnQ@z> (raw)
In-Reply-To: <54EFBF9D.4020004@gmail.com>
On 02/26/2015 06:51 PM, David Daney wrote:
>
> That's not really what I meant in my previous response on the subject.
> When I said:
>
> Why not just use RI for everything, instead of taking up two bits
> to represent a single binary concept?
>
> For the case where there is no RI hardware active, it is a purely
> software bit and you can easily invert the meaning and just have a
> _PAGE_NO_READ bit.
>
> I envisioned something like:
>
> 64-bit, all revisions: CCC D V G RI XI [S H] M A W P
> 32-bit, all revisions: CCC D V G RI XI M A W P
>
Which is what I implemented. I now only use one bit that functions
either as _PAGE_READ or _PAGE_READ_ONLY depending on the RI/XI
functionality present. Did you bother to read the code and understand
it, or just look at the commit message?
Steve
next prev parent reply other threads:[~2015-02-27 3:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-27 0:16 [PATCH V7 0/3] Add support for eXtended Physical Addressing Steven J. Hill
2015-02-27 0:16 ` [PATCH V7 1/3] MIPS: Rearrange PTE bits into fixed positions Steven J. Hill
2015-02-27 0:51 ` David Daney
2015-02-27 3:38 ` Steven J. Hill [this message]
2015-02-27 3:38 ` Steven J. Hill
2015-02-27 17:52 ` David Daney
2015-02-27 19:04 ` Steven J. Hill
2015-02-27 19:04 ` Steven J. Hill
2015-02-27 19:20 ` David Daney
2015-07-09 4:23 ` Huacai Chen
2015-02-27 0:16 ` [PATCH V7 2/3] MIPS: Add support for XPA Steven J. Hill
2015-02-27 0:16 ` [PATCH V7 3/3] MIPS: XPA: Add new configuration file Steven J. Hill
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