From: Markos Chandras <Markos.Chandras@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>, David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] MIPS: mm: tlbex: Replace cpu_has_mips_r2_exec_hazard with cpu_has_mips_r2_r6
Date: Fri, 13 Mar 2015 15:41:45 +0000 [thread overview]
Message-ID: <55030539.6070803@imgtec.com> (raw)
In-Reply-To: <20150313144443.GA12977@linux-mips.org>
Hi,
On 03/13/2015 02:44 PM, Ralf Baechle wrote:
> On Fri, Mar 13, 2015 at 09:18:08AM +0000, Markos Chandras wrote:
>
>> Commit 77f3ee59ee7cf ("MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard
>> for the EHB instruction") replaced cpu_has_mips_r2 with
>> cpu_has_mips_r2_exec_hazard to indicate whether the ISA has the EHB
>> instruction. However, the meaning of the cpu_has_mips_r2_exec_hazard
>> is different. It was meant to be used as an indication on whether the
>> running processor needs to run the EHB instruction instead of checking
>> whether the EHB is available on the ISA. This broke processors that do
>> not define cpu_has_mips_r2_exec_hazard. We fix this by replacing the
>> said macro with cpu_has_mips_r2_r6 which covers R2 and R6 processors.
>>
>> Fixes: 77f3ee59ee7cf ("MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction")
>> Cc: David Daney <david.daney@cavium.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>
> Either of this David's revert or this patch applied will leave
> cpu_has_mips_r2_exec_hazard unused which at a glance doesn't seem to
> be right and defeats David's old patches 9e290a19 / 41f0e4d0 from working.
>
> cpu_has_mips_r2_exec_hazard was made unused by 625c0a21 which I think
> should be reverted and cpu_has_mips_r2_exec_hazard be defined to be something
> like
Indeed that looks an old regression. Thanks for spotting that.
>
> #define cpu_has_mips_r2_exec_hazard \
> ({ \
> int __res; \
> \
> switch (current_cpu_type()) { \
> case CPU_M14KC: \
> case CPU74K: \
More MIPS/IMG cores need to be added here but ok
> case CPU_CAVIUM_OCTEON: \
> case CPU_CAVIUM_OCTEON_PLUS: \
> case CPU_CAVIUM_OCTEON2: \
> case CPU_CAVIUM_OCTEON3: \
> __res = 0; \
> break; \
> \
> default: \
> __res = 1; \
> } \
> \
> __res; \
> })
>
> ?
Overall, that looks like a good solution to me
--
markos
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <Markos.Chandras@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] MIPS: mm: tlbex: Replace cpu_has_mips_r2_exec_hazard with cpu_has_mips_r2_r6
Date: Fri, 13 Mar 2015 15:41:45 +0000 [thread overview]
Message-ID: <55030539.6070803@imgtec.com> (raw)
Message-ID: <20150313154145.muNbAGsaci2nESH5QV1f7CRAxbI08-UckyFotGfhxmQ@z> (raw)
In-Reply-To: <20150313144443.GA12977@linux-mips.org>
Hi,
On 03/13/2015 02:44 PM, Ralf Baechle wrote:
> On Fri, Mar 13, 2015 at 09:18:08AM +0000, Markos Chandras wrote:
>
>> Commit 77f3ee59ee7cf ("MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard
>> for the EHB instruction") replaced cpu_has_mips_r2 with
>> cpu_has_mips_r2_exec_hazard to indicate whether the ISA has the EHB
>> instruction. However, the meaning of the cpu_has_mips_r2_exec_hazard
>> is different. It was meant to be used as an indication on whether the
>> running processor needs to run the EHB instruction instead of checking
>> whether the EHB is available on the ISA. This broke processors that do
>> not define cpu_has_mips_r2_exec_hazard. We fix this by replacing the
>> said macro with cpu_has_mips_r2_r6 which covers R2 and R6 processors.
>>
>> Fixes: 77f3ee59ee7cf ("MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction")
>> Cc: David Daney <david.daney@cavium.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>
> Either of this David's revert or this patch applied will leave
> cpu_has_mips_r2_exec_hazard unused which at a glance doesn't seem to
> be right and defeats David's old patches 9e290a19 / 41f0e4d0 from working.
>
> cpu_has_mips_r2_exec_hazard was made unused by 625c0a21 which I think
> should be reverted and cpu_has_mips_r2_exec_hazard be defined to be something
> like
Indeed that looks an old regression. Thanks for spotting that.
>
> #define cpu_has_mips_r2_exec_hazard \
> ({ \
> int __res; \
> \
> switch (current_cpu_type()) { \
> case CPU_M14KC: \
> case CPU74K: \
More MIPS/IMG cores need to be added here but ok
> case CPU_CAVIUM_OCTEON: \
> case CPU_CAVIUM_OCTEON_PLUS: \
> case CPU_CAVIUM_OCTEON2: \
> case CPU_CAVIUM_OCTEON3: \
> __res = 0; \
> break; \
> \
> default: \
> __res = 1; \
> } \
> \
> __res; \
> })
>
> ?
Overall, that looks like a good solution to me
--
markos
next prev parent reply other threads:[~2015-03-13 15:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 22:52 [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction" David Daney
2015-02-24 1:10 ` Maciej W. Rozycki
2015-03-11 8:28 ` Markos Chandras
2015-03-11 8:28 ` Markos Chandras
2015-03-11 16:51 ` David Daney
2015-03-13 9:18 ` [PATCH] MIPS: mm: tlbex: Replace cpu_has_mips_r2_exec_hazard with cpu_has_mips_r2_r6 Markos Chandras
2015-03-13 9:18 ` Markos Chandras
2015-03-13 14:44 ` Ralf Baechle
2015-03-13 15:41 ` Markos Chandras [this message]
2015-03-13 15:41 ` Markos Chandras
2015-03-26 20:52 ` Maciej W. Rozycki
2015-03-13 15:46 ` David Daney
2015-03-13 15:46 ` David Daney
2015-03-13 17:10 ` Ralf Baechle
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