Re: [PATCH 6/9] clk: pistachio: Propagate rate changes in the MIPS PLL clock sub-tree

[Ezequiel Garcia <ezequiel.garcia@imgtec.com>]

On 05/22/2015 02:42 PM, Andrew Bresticker wrote:
> On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
> <ezequiel.garcia@imgtec.com> wrote:
>> This commit passes CLK_SET_RATE_PARENT to the "mips_div",
>> "mips_internal_div", and "mips_pll_mux" clocks. This flag is needed for the
>> "mips" clock to propagate rate changes up to the "mips_pll" root clock.
>>
>> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
>> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
> 
> IIRC the clk core will prefer changing a downstream divider over
> propagating the rate change up another level.  So, for example, if
> MIPS_PLL is initially 400Mhz and we request a MIPS rate of 200Mhz,
> we'll change the first intermediate divider to /2 rather than
> propagate the rate change up to MIPS_PLL.  Wouldn't it be more
> power-efficient to set the MIPS_PLL directly to the requested rate
> rather than using external dividers to divide it down?
> 

Indeed.

Do you think we still want to be able to change the MIPS clk rate and
propagate the change up to the PLL? Otherwise, I'll drop this patch and
I'll drop the DIV_F and MUX_F macro patches.

-- 
Ezequiel