* [PATCH 01/10] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-13 21:58 ` [PATCH 02/10] MIPS: dts: qca: ar9132: fix typo: "ppl" -> "pll" Antony Pavlov
` (8 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, devicetree
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Alban Bedel <albeu@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
index e0fc2c1..ae99f22 100644
--- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+- compatible: has to be "qca,<soctype>-pll" and one of the following
fallbacks:
- "qca,ar7100-pll"
- "qca,ar7240-pll"
@@ -21,7 +21,7 @@ Optional properties:
Example:
- memory-controller@18050000 {
+ pll-controller@18050000 {
compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 02/10] MIPS: dts: qca: ar9132: fix typo: "ppl" -> "pll"
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
2016-02-13 21:58 ` [PATCH 01/10] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-22 2:54 ` Rob Herring
2016-02-13 21:58 ` [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation Antony Pavlov
` (7 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, devicetree
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 2 +-
arch/mips/boot/dts/qca/ar9132.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
index ae99f22..241fb05 100644
--- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -22,7 +22,7 @@ Optional properties:
Example:
pll-controller@18050000 {
- compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
+ compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
clock-names = "ref";
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
index 3ad4ba9..3c2ed9e 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -83,7 +83,7 @@
};
pll: pll-controller@18050000 {
- compatible = "qca,ar9132-ppl",
+ compatible = "qca,ar9132-pll",
"qca,ar9130-pll";
reg = <0x18050000 0x20>;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 02/10] MIPS: dts: qca: ar9132: fix typo: "ppl" -> "pll"
2016-02-13 21:58 ` [PATCH 02/10] MIPS: dts: qca: ar9132: fix typo: "ppl" -> "pll" Antony Pavlov
@ 2016-02-22 2:54 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2016-02-22 2:54 UTC (permalink / raw)
To: Antony Pavlov
Cc: linux-mips, Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, devicetree
On Sun, Feb 14, 2016 at 12:58:09AM +0300, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
> Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 2 +-
> arch/mips/boot/dts/qca/ar9132.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
I'd just roll this into the previous patch.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
2016-02-13 21:58 ` [PATCH 01/10] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos Antony Pavlov
2016-02-13 21:58 ` [PATCH 02/10] MIPS: dts: qca: ar9132: fix typo: "ppl" -> "pll" Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-14 13:44 ` Marek Vasut
2016-02-13 21:58 ` [PATCH 04/10] MIPS: ath79: Fix the ar913x reference clock rate Antony Pavlov
` (6 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, Weijie Gao
From: Weijie Gao <hackpascal@gmail.com>
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with
default FB and REF_DIV values.
Tested on AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Alban Bedel <albeu@free.fr>
[albeu@free.fr: Fixed the commit log message]
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/ath79/clock.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117c..ed28465 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -26,7 +26,7 @@
#include "common.h"
#define AR71XX_BASE_FREQ 40000000
-#define AR724X_BASE_FREQ 5000000
+#define AR724X_BASE_FREQ 40000000
#define AR913X_BASE_FREQ 5000000
static struct clk *clks[3];
@@ -103,8 +103,8 @@ static void __init ar724x_clocks_init(void)
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
freq = div * ref_rate;
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
- freq *= div;
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
+ freq /= div;
cpu_rate = freq;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation
2016-02-13 21:58 ` [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation Antony Pavlov
@ 2016-02-14 13:44 ` Marek Vasut
2016-02-14 17:02 ` Antony Pavlov
0 siblings, 1 reply; 20+ messages in thread
From: Marek Vasut @ 2016-02-14 13:44 UTC (permalink / raw)
To: Antony Pavlov, linux-mips
Cc: Ralf Baechle, Alban Bedel, Wills Wang, Daniel Schwierzeck,
Weijie Gao
On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> From: Weijie Gao <hackpascal@gmail.com>
>
> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> input clock as the REF_CLK instead of 5MHz.
Can't the AR71xx also use 25MHz clock source ?
> The correct CPU PLL calculation procedure is as follows:
> CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
[...]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation
2016-02-14 13:44 ` Marek Vasut
@ 2016-02-14 17:02 ` Antony Pavlov
2016-02-14 18:45 ` Marek Vasut
0 siblings, 1 reply; 20+ messages in thread
From: Antony Pavlov @ 2016-02-14 17:02 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-mips, Ralf Baechle, Alban Bedel, Wills Wang,
Daniel Schwierzeck, Weijie Gao
On Sun, 14 Feb 2016 14:44:36 +0100
Marek Vasut <marex@denx.de> wrote:
> On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> > From: Weijie Gao <hackpascal@gmail.com>
> >
> > According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> > input clock as the REF_CLK instead of 5MHz.
>
> Can't the AR71xx also use 25MHz clock source ?
I have just googled AR7242 datasheet.
I states that only 40 MHz reference clock is used.
> > The correct CPU PLL calculation procedure is as follows:
> > CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
>
> [...]
--
--
Best regards,
Antony Pavlov
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation
2016-02-14 17:02 ` Antony Pavlov
@ 2016-02-14 18:45 ` Marek Vasut
0 siblings, 0 replies; 20+ messages in thread
From: Marek Vasut @ 2016-02-14 18:45 UTC (permalink / raw)
To: Antony Pavlov
Cc: linux-mips, Ralf Baechle, Alban Bedel, Wills Wang,
Daniel Schwierzeck, Weijie Gao
On 02/14/2016 06:02 PM, Antony Pavlov wrote:
> On Sun, 14 Feb 2016 14:44:36 +0100
> Marek Vasut <marex@denx.de> wrote:
>
>> On 02/13/2016 10:58 PM, Antony Pavlov wrote:
>>> From: Weijie Gao <hackpascal@gmail.com>
>>>
>>> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
>>> input clock as the REF_CLK instead of 5MHz.
>>
>> Can't the AR71xx also use 25MHz clock source ?
>
>
> I have just googled AR7242 datasheet.
> I states that only 40 MHz reference clock is used.
Gotcha, so it's only the later chips which can do both.
Thanks!
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 04/10] MIPS: ath79: Fix the ar913x reference clock rate
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (2 preceding siblings ...)
2016-02-13 21:58 ` [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-13 21:58 ` [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node Antony Pavlov
` (5 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck
From: Alban Bedel <albeu@free.fr>
The reference clock on ar913x is at 40MHz and not 5MHz. The current
implementation use the wrong reference rate because it doesn't take
the PLL divider in account. But if we fix the code to use the divider
it becomes identical with the implementation for ar724x, so just drop
the broken ar913x implementation.
Signed-off-by: Alban Bedel <albeu@free.fr>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/ath79/clock.c | 38 +-------------------------------------
1 file changed, 1 insertion(+), 37 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index ed28465..618dfd7 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -27,7 +27,6 @@
#define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 40000000
-#define AR913X_BASE_FREQ 5000000
static struct clk *clks[3];
static struct clk_onecell_data clk_data = {
@@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void)
clk_add_alias("uart", NULL, "ahb", NULL);
}
-static void __init ar913x_clocks_init(void)
-{
- unsigned long ref_rate;
- unsigned long cpu_rate;
- unsigned long ddr_rate;
- unsigned long ahb_rate;
- u32 pll;
- u32 freq;
- u32 div;
-
- ref_rate = AR913X_BASE_FREQ;
- pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
-
- div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
- freq = div * ref_rate;
-
- cpu_rate = freq;
-
- div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
- ddr_rate = freq / div;
-
- div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
- ahb_rate = cpu_rate / div;
-
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
-}
-
static void __init ar933x_clocks_init(void)
{
unsigned long ref_rate;
@@ -443,10 +409,8 @@ void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
ar71xx_clocks_init();
- else if (soc_is_ar724x())
+ else if (soc_is_ar724x() || soc_is_ar913x())
ar724x_clocks_init();
- else if (soc_is_ar913x())
- ar913x_clocks_init();
else if (soc_is_ar933x())
ar933x_clocks_init();
else if (soc_is_ar934x())
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (3 preceding siblings ...)
2016-02-13 21:58 ` [PATCH 04/10] MIPS: ath79: Fix the ar913x reference clock rate Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-14 13:46 ` Marek Vasut
2016-02-13 21:58 ` [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes Antony Pavlov
` (4 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, devicetree
The TP-LINK TL-WR1043ND board has only one serial port,
so replacing the default of 0 with 0 does nothing useful.
Moreover, the correct name for aliases node is "aliases" not "alias".
An overview of the "aliases" node usage can be found
on the device tree usage page at devicetree.org [1].
Also please see chapter 3.3 ("Aliases node") of the ePAPR 1.1 [2].
[1] http://devicetree.org/Device_Tree_Usage#aliases_Node
[2] https://www.power.org/documentation/epapr-version-1-1/
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Alban Bedel <albeu@free.fr>
Cc: Alban Bedel <albeu@free.fr>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
index e535ee3..c3069c3 100644
--- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
@@ -9,10 +9,6 @@
compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
model = "TP-Link TL-WR1043ND Version 1";
- alias {
- serial0 = "/ahb/apb/uart@18020000";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x2000000>;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node
2016-02-13 21:58 ` [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node Antony Pavlov
@ 2016-02-14 13:46 ` Marek Vasut
2016-02-15 8:36 ` Alban
2016-02-15 9:54 ` Antony Pavlov
0 siblings, 2 replies; 20+ messages in thread
From: Marek Vasut @ 2016-02-14 13:46 UTC (permalink / raw)
To: Antony Pavlov, linux-mips
Cc: Ralf Baechle, Alban Bedel, Wills Wang, Daniel Schwierzeck,
devicetree
On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> The TP-LINK TL-WR1043ND board has only one serial port,
> so replacing the default of 0 with 0 does nothing useful.
I'd suggest to keep the aliases node, since it can be used by other
non-Linux systems to access the serial port 0 . This might be useful in
case you add some additional UART chip(s) too.
[...]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node
2016-02-14 13:46 ` Marek Vasut
@ 2016-02-15 8:36 ` Alban
2016-02-15 9:54 ` Antony Pavlov
1 sibling, 0 replies; 20+ messages in thread
From: Alban @ 2016-02-15 8:36 UTC (permalink / raw)
To: Marek Vasut
Cc: Aban Bedel, Antony Pavlov, linux-mips, Ralf Baechle, Wills Wang,
Daniel Schwierzeck, devicetree
On Sun, 14 Feb 2016 14:46:05 +0100
Marek Vasut <marex@denx.de> wrote:
> On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> > The TP-LINK TL-WR1043ND board has only one serial port,
> > so replacing the default of 0 with 0 does nothing useful.
>
> I'd suggest to keep the aliases node, since it can be used by other
> non-Linux systems to access the serial port 0 . This might be useful in
> case you add some additional UART chip(s) too.
I have no strong preference, the DT people preferred to see it removed
has it had been never used. I agree other systems might need it, but if
you hack the board to add some stuff you will need your own DTS. So it
make no sense to take such eventual hack in consideration here.
Alban
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node
2016-02-14 13:46 ` Marek Vasut
2016-02-15 8:36 ` Alban
@ 2016-02-15 9:54 ` Antony Pavlov
1 sibling, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-15 9:54 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-mips, Ralf Baechle, Alban Bedel, Wills Wang,
Daniel Schwierzeck, devicetree, David Daney
On Sun, 14 Feb 2016 14:46:05 +0100
Marek Vasut <marex@denx.de> wrote:
> On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> > The TP-LINK TL-WR1043ND board has only one serial port,
> > so replacing the default of 0 with 0 does nothing useful.
>
> I'd suggest to keep the aliases node, since it can be used by other
> non-Linux systems to access the serial port 0 . This might be useful in
> case you add some additional UART chip(s) too.
>
> [...]
I have already submitted the patch which keeps the aliases node:
https://www.linux-mips.org/archives/linux-mips/2016-01/msg00306.html
It was David Daney who proposed to drop unused aliases node:
https://www.linux-mips.org/archives/linux-mips/2016-01/msg00353.html
--
Best regards,
Antony Pavlov
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (4 preceding siblings ...)
2016-02-13 21:58 ` [PATCH 05/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: drop unused alias node Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-14 13:47 ` Marek Vasut
2016-02-14 21:24 ` Alban
2016-02-13 21:58 ` [PATCH 07/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: use "ref" for reference clock name Antony Pavlov
` (3 subsequent siblings)
9 siblings, 2 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, Sascha Hauer, Rob Herring, Frank Rowand,
Grant Likely, devicetree
Here are some Sascha Hauer's arguments for using aliases in the dts
files:
- using aliases reduces the number of indentations in dts files;
- dts files become independent of the layout of the dtsi files
(it becomes possible to introduce another bus {} hierarchy between
a toplevel bus and the devices when you have to);
- less chances for typos. if &i2c2 does not exist you get an error.
If instead you duplicate the whole path in the dts file a typo
in the path will just create another node.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
arch/mips/boot/dts/qca/ar9132.dtsi | 6 +-
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 82 ++++++++++++------------
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
index 3c2ed9e..511cb4d 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -52,7 +52,7 @@
#qca,ddr-wb-channel-cells = <1>;
};
- uart@18020000 {
+ uart: uart@18020000 {
compatible = "ns8250";
reg = <0x18020000 0x20>;
interrupts = <3>;
@@ -125,7 +125,7 @@
};
};
- usb@1b000100 {
+ usb: usb@1b000100 {
compatible = "qca,ar7100-ehci", "generic-ehci";
reg = <0x1b000100 0x100>;
@@ -140,7 +140,7 @@
status = "disabled";
};
- spi@1f000000 {
+ spi: spi@1f000000 {
compatible = "qca,ar9132-spi", "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
index c3069c3..9528ebd 100644
--- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
@@ -22,51 +22,10 @@
ahb {
apb {
- uart@18020000 {
- status = "okay";
- };
-
pll-controller@18050000 {
clocks = <&extosc>;
};
};
-
- usb@1b000100 {
- status = "okay";
- };
-
- spi@1f000000 {
- status = "okay";
- num-cs = <1>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25sl064a";
- reg = <0>;
- spi-max-frequency = <25000000>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x000000 0x020000>;
- };
-
- partition@1 {
- label = "firmware";
- reg = <0x020000 0x7D0000>;
- };
-
- partition@2 {
- label = "art";
- reg = <0x7F0000 0x010000>;
- read-only;
- };
- };
- };
- };
-
- usb-phy {
- status = "okay";
};
gpio-keys {
@@ -114,3 +73,44 @@
};
};
};
+
+&uart {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+ num-cs = <1>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25sl064a";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x000000 0x020000>;
+ };
+
+ partition@1 {
+ label = "firmware";
+ reg = <0x020000 0x7D0000>;
+ };
+
+ partition@2 {
+ label = "art";
+ reg = <0x7F0000 0x010000>;
+ read-only;
+ };
+ };
+};
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes
2016-02-13 21:58 ` [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes Antony Pavlov
@ 2016-02-14 13:47 ` Marek Vasut
2016-02-14 21:24 ` Alban
1 sibling, 0 replies; 20+ messages in thread
From: Marek Vasut @ 2016-02-14 13:47 UTC (permalink / raw)
To: Antony Pavlov, linux-mips
Cc: Ralf Baechle, Alban Bedel, Wills Wang, Daniel Schwierzeck,
Sascha Hauer, Rob Herring, Frank Rowand, Grant Likely, devicetree
On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> Here are some Sascha Hauer's arguments for using aliases in the dts
> files:
>
> - using aliases reduces the number of indentations in dts files;
>
> - dts files become independent of the layout of the dtsi files
> (it becomes possible to introduce another bus {} hierarchy between
> a toplevel bus and the devices when you have to);
>
> - less chances for typos. if &i2c2 does not exist you get an error.
> If instead you duplicate the whole path in the dts file a typo
> in the path will just create another node.
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Frank Rowand <frowand.list@gmail.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
Acked-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes
2016-02-13 21:58 ` [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes Antony Pavlov
2016-02-14 13:47 ` Marek Vasut
@ 2016-02-14 21:24 ` Alban
1 sibling, 0 replies; 20+ messages in thread
From: Alban @ 2016-02-14 21:24 UTC (permalink / raw)
To: Antony Pavlov
Cc: Aban Bedel, linux-mips, Ralf Baechle, Marek Vasut, Wills Wang,
Daniel Schwierzeck, Sascha Hauer, Rob Herring, Frank Rowand,
Grant Likely, devicetree
On Sun, 14 Feb 2016 00:58:13 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:
> Here are some Sascha Hauer's arguments for using aliases in the dts
> files:
>
> - using aliases reduces the number of indentations in dts files;
>
> - dts files become independent of the layout of the dtsi files
> (it becomes possible to introduce another bus {} hierarchy between
> a toplevel bus and the devices when you have to);
>
> - less chances for typos. if &i2c2 does not exist you get an error.
> If instead you duplicate the whole path in the dts file a typo
> in the path will just create another node.
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Frank Rowand <frowand.list@gmail.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
> arch/mips/boot/dts/qca/ar9132.dtsi | 6 +-
> arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 82 ++++++++++++------------
> 2 files changed, 44 insertions(+), 44 deletions(-)
>
> diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
> index 3c2ed9e..511cb4d 100644
> --- a/arch/mips/boot/dts/qca/ar9132.dtsi
> +++ b/arch/mips/boot/dts/qca/ar9132.dtsi
> @@ -52,7 +52,7 @@
> #qca,ddr-wb-channel-cells = <1>;
> };
>
> - uart@18020000 {
> + uart: uart@18020000 {
> compatible = "ns8250";
> reg = <0x18020000 0x20>;
> interrupts = <3>;
Please also add a label for the watchdog, then all devices would be
covered.
> @@ -125,7 +125,7 @@
> };
> };
>
> - usb@1b000100 {
> + usb: usb@1b000100 {
> compatible = "qca,ar7100-ehci", "generic-ehci";
> reg = <0x1b000100 0x100>;
>
> @@ -140,7 +140,7 @@
> status = "disabled";
> };
>
> - spi@1f000000 {
> + spi: spi@1f000000 {
> compatible = "qca,ar9132-spi", "qca,ar7100-spi";
> reg = <0x1f000000 0x10>;
>
> diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
> index c3069c3..9528ebd 100644
> --- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
> +++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
> @@ -22,51 +22,10 @@
>
> ahb {
> apb {
> - uart@18020000 {
> - status = "okay";
> - };
> -
> pll-controller@18050000 {
> clocks = <&extosc>;
> };
> };
Better use a reference for the PLL clock too.
> -
> - usb@1b000100 {
> - status = "okay";
> - };
> -
> - spi@1f000000 {
> - status = "okay";
> - num-cs = <1>;
> -
> - flash@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "s25sl064a";
> - reg = <0>;
> - spi-max-frequency = <25000000>;
> -
> - partition@0 {
> - label = "u-boot";
> - reg = <0x000000 0x020000>;
> - };
> -
> - partition@1 {
> - label = "firmware";
> - reg = <0x020000 0x7D0000>;
> - };
> -
> - partition@2 {
> - label = "art";
> - reg = <0x7F0000 0x010000>;
> - read-only;
> - };
> - };
> - };
> - };
> -
> - usb-phy {
> - status = "okay";
> };
>
> gpio-keys {
> @@ -114,3 +73,44 @@
> };
> };
> };
> +
> +&uart {
> + status = "okay";
> +};
> +
> +&usb {
> + status = "okay";
> +};
> +
> +&usb_phy {
> + status = "okay";
> +};
> +
> +&spi {
> + status = "okay";
> + num-cs = <1>;
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "s25sl064a";
> + reg = <0>;
> + spi-max-frequency = <25000000>;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0x000000 0x020000>;
> + };
> +
> + partition@1 {
> + label = "firmware";
> + reg = <0x020000 0x7D0000>;
> + };
> +
> + partition@2 {
> + label = "art";
> + reg = <0x7F0000 0x010000>;
> + read-only;
> + };
Looses partitions like this are now deprecated, we could take the
opportunity to move to the new scheme. We just have to put all the
"partition" nodes under a "partitions" node with a proper compatible and
#address-cells and #size-cells.
Alban
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 07/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: use "ref" for reference clock name
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (5 preceding siblings ...)
2016-02-13 21:58 ` [PATCH 06/10] MIPS: dts: qca: ar9132: use short references for uart, usb and spi nodes Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-13 21:58 ` [RFC 08/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (2 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, Michael Turquette, linux-clk, Rob Herring,
devicetree
Current ath79 clock.c code does not read reference clock and
pll setup from devicetree. The ar724x_clocks_init() function
recreates the clocks from scratch so devicetree clock
information is dropped. After adding the code which picked up
reference clock from devicetree I have found
that kernel does not boot anymore. The SPI and UART drivers
can't get clk; here are a bootlog error messages:
of_serial: probe of 18020000.uart failed with error -22
ath79-spi: probe of 1f000000.spi failed with error -22
The problem is that clock code assumes that reference clock
name is "ref" by current dts-file uses another name: "oscillator".
This patch fixes the problem by changing external oscillator
dt node name to "ref".
Please note that there is an alternative solution for the problem:
> --- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
> +++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
> @@ -16,6 +16,7 @@
>
> extosc: oscillator {
> compatible = "fixed-clock";
> + clock-output-names = "ref";
> #clock-cells = <0>;
> clock-frequency = <40000000>;
> };
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
---
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
index 9528ebd..bae72da 100644
--- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
@@ -14,7 +14,7 @@
reg = <0x0 0x2000000>;
};
- extosc: oscillator {
+ extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [RFC 08/10] MIPS: ath79: update devicetree support for AR9132
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (6 preceding siblings ...)
2016-02-13 21:58 ` [PATCH 07/10] MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: use "ref" for reference clock name Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-13 21:58 ` [RFC 09/10] MIPS: ath79: setup.c: disable platform code for OF boards Antony Pavlov
2016-02-13 21:58 ` [RFC 10/10] WIP: MIPS: ath79: add tl-wr1043nd{,no-dt}_defconfig Antony Pavlov
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck, Gabor Juhos, Michael Turquette, Stephen Boyd,
Rob Herring, linux-clk, devicetree
Current ath79 clock.c code does not read reference clock and
pll setup from devicetree. E.g. you can set any clock rate value
in board DTS but it will have no effect on the real clk calculation.
This patch fixes some AR9132 devicetree clock support deffects:
* clk initialization function ath79_clocks_init_dt_ng()
is introduced; it actually gets reference clock
and pll block base register address from devicetree;
* pll register parsing code moved to the separate
ar724x_clk_init() function; this function
can be called from platform code or from devicetree code;
* introduces include/dt-bindings/clock/ath79-clk.h,
so we can use human-readable macro for clks naming;
The same approach can be used for adding AR9331 devicetree support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
arch/mips/ath79/clock.c | 138 +++++++++++++++++++++++++++-------
arch/mips/boot/dts/qca/ar9132.dtsi | 8 +-
include/dt-bindings/clock/ath79-clk.h | 20 +++++
3 files changed, 134 insertions(+), 32 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 618dfd7..58ba7d7 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -18,12 +18,16 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/ath79-clk.h>
#include <asm/div64.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
+#include "machtypes.h"
#define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 40000000
@@ -86,37 +90,66 @@ static void __init ar71xx_clocks_init(void)
clk_add_alias("uart", NULL, "ahb", NULL);
}
+static struct clk *clks_ng[ATH79_CLK_END];
+static struct clk_onecell_data clk_data_ng = {
+ .clks = clks_ng,
+ .clk_num = ARRAY_SIZE(clks_ng),
+};
+
+static struct clk * __init ath79_reg_ffclk(const char *name,
+ const char *parent_name, unsigned int mult, unsigned int div)
+{
+ struct clk *clk;
+ int err;
+
+ clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+ if (!clk)
+ panic("failed to allocate %s clock structure", name);
+
+ /*
+ * dt-enabled linux does not need clk_register_clkdev()
+ * but it makes happy plat_time_init() from arch/mips/ath79/setup.c
+ */
+ err = clk_register_clkdev(clk, name, NULL);
+ if (err)
+ panic("unable to register %s clock device", name);
+
+ return clk;
+}
+
+static struct clk_onecell_data * __init ar724x_clk_init(
+ struct clk *ref_clk, void __iomem *pll_base)
+{
+ u32 pll;
+ u32 mult, div, ddr_div, ahb_div;
+
+ pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
+
+ mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
+
+ ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
+ ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
+
+ clks_ng[ATH79_CLK_REF] = ref_clk;
+ clks_ng[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
+ clks_ng[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
+ clks_ng[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
+
+ return &clk_data_ng;
+}
+
static void __init ar724x_clocks_init(void)
{
- unsigned long ref_rate;
- unsigned long cpu_rate;
- unsigned long ddr_rate;
- unsigned long ahb_rate;
- u32 pll;
- u32 freq;
- u32 div;
+ struct clk *ref_clk;
+ struct clk_onecell_data *clk_data;
- ref_rate = AR724X_BASE_FREQ;
- pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
+ ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
- div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
- freq = div * ref_rate;
+ clk_data = ar724x_clk_init(ref_clk, ath79_pll_base);
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
- freq /= div;
-
- cpu_rate = freq;
-
- div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
- ddr_rate = freq / div;
-
- div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
- ahb_rate = cpu_rate / div;
-
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
+ clk_register_clkdev(clk_data->clks[ATH79_CLK_REF], "ref", NULL);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
@@ -407,6 +440,11 @@ static void __init qca955x_clocks_init(void)
void __init ath79_clocks_init(void)
{
+ if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
+ of_clk_init(NULL);
+ return;
+ }
+
if (soc_is_ar71xx())
ar71xx_clocks_init();
else if (soc_is_ar724x() || soc_is_ar913x())
@@ -419,8 +457,6 @@ void __init ath79_clocks_init(void)
qca955x_clocks_init();
else
BUG();
-
- of_clk_init(NULL);
}
unsigned long __init
@@ -447,8 +483,52 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
+
+static void __init ath79_clocks_init_dt_ng(struct device_node *np)
+{
+ struct clk *ref_clk;
+ void __iomem *pll_base;
+ struct clk_onecell_data *clk_data;
+
+ ref_clk = of_clk_get(np, 0);
+ if (IS_ERR(ref_clk)) {
+ pr_err("%s: of_clk_get failed\n", np->full_name);
+ goto err;
+ }
+
+ pll_base = of_iomap(np, 0);
+ if (!pll_base) {
+ pr_err("%s: can't map pll registers\n", np->full_name);
+ goto err_clk;
+ }
+
+ clk_data = ar724x_clk_init(ref_clk, pll_base);
+ if (!clk_data) {
+ pr_err("%s: clk_init failed\n", np->full_name);
+ goto err_clk;
+ }
+
+ if (of_clk_add_provider(np, of_clk_src_onecell_get, clk_data)) {
+ pr_err("%s: could not register clk provider\n", np->full_name);
+ goto err_clk;
+ }
+
+ /*
+ * dt-enabled linux does not need clk_register_clkdev()
+ * but it makes happy plat_time_init() from arch/mips/ath79/setup.c
+ */
+ clk_register_clkdev(clk_data->clks[ATH79_CLK_REF], "ref", NULL);
+
+ return;
+
+err_clk:
+ clk_put(ref_clk);
+
+err:
+ return;
+}
+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
#endif
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
index 511cb4d..fb844b8 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/clock/ath79-clk.h>
+
/ {
compatible = "qca,ar9132";
@@ -57,7 +59,7 @@
reg = <0x18020000 0x20>;
interrupts = <3>;
- clocks = <&pll 2>;
+ clocks = <&pll ATH79_CLK_AHB>;
clock-names = "uart";
reg-io-width = <4>;
@@ -100,7 +102,7 @@
interrupts = <4>;
- clocks = <&pll 2>;
+ clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
@@ -144,7 +146,7 @@
compatible = "qca,ar9132-spi", "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
- clocks = <&pll 2>;
+ clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
status = "disabled";
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 0000000..af64e36
--- /dev/null
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_REF 0
+#define ATH79_CLK_CPU 1
+#define ATH79_CLK_DDR 2
+#define ATH79_CLK_AHB 3
+
+#define ATH79_CLK_END 4
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [RFC 09/10] MIPS: ath79: setup.c: disable platform code for OF boards
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (7 preceding siblings ...)
2016-02-13 21:58 ` [RFC 08/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
2016-02-13 21:58 ` [RFC 10/10] WIP: MIPS: ath79: add tl-wr1043nd{,no-dt}_defconfig Antony Pavlov
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck
For OF boards we have to skip platform initialization code
so we can prove that OF code do all necessary initialization.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
---
arch/mips/ath79/setup.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 99ab4bb..d65d161 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -206,15 +206,16 @@ void __init plat_mem_setup(void)
else if (fw_arg0 == -2)
__dt_setup_arch((void *)fw_arg1);
- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
- AR71XX_RESET_SIZE);
- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
- AR71XX_PLL_SIZE);
- ath79_detect_sys_type();
- ath79_ddr_ctrl_init();
+ if (mips_machtype != ATH79_MACH_GENERIC_OF) {
+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
+ AR71XX_RESET_SIZE);
+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
+ AR71XX_PLL_SIZE);
+ ath79_detect_sys_type();
+ ath79_ddr_ctrl_init();
- if (mips_machtype != ATH79_MACH_GENERIC_OF)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+ }
_machine_restart = ath79_restart;
_machine_halt = ath79_halt;
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [RFC 10/10] WIP: MIPS: ath79: add tl-wr1043nd{,no-dt}_defconfig
2016-02-13 21:58 [PATCH 00/10] MIPS: ath79: update devicetree support for AR9132 Antony Pavlov
` (8 preceding siblings ...)
2016-02-13 21:58 ` [RFC 09/10] MIPS: ath79: setup.c: disable platform code for OF boards Antony Pavlov
@ 2016-02-13 21:58 ` Antony Pavlov
9 siblings, 0 replies; 20+ messages in thread
From: Antony Pavlov @ 2016-02-13 21:58 UTC (permalink / raw)
To: linux-mips
Cc: Ralf Baechle, Alban Bedel, Marek Vasut, Wills Wang,
Daniel Schwierzeck
This commit adds defconfig files for testing linux kernel
on TP-LINK WE1043ND router. Two configurations are proposed:
one with device tree support and another one legacy platform
configuration.
This patchseries relies on additonal patches by Alban Bedel:
* MIPS: OF: Rework the appended DTB handling to keep the PROM arguments
https://github.com/AlbanBedel/linux/commit/3e1bb5db49a9da1d5d9c90d345fd114f00596c19
* MIPS: ath79: Add support for DTB passed using the UHI boot protocol
https://github.com/AlbanBedel/linux/commit/b0229b82f84c3e054308eb481d0f4a782fc8ac41
* MIPS: ath79: Remove the builtin DTB support
https://github.com/AlbanBedel/linux/commit/0b8843b069e525db690c253e03b7a15bc1d1f0df
* MIPS: ath79: Add the TL-WR1043ND as legacy device for testing
https://github.com/AlbanBedel/linux/commit/5386bf83c03bfc41fc6a9394e1424544806e36f7
Here is a small instruction:
1. download rootfs.mipsI.cpio image into your linux kernel
source root dir.
$ wget https://github.com/frantony/linux/raw/c95a5953e3dd96ad304de515f79acb555e0bc24e/rootfs.mipsI.cpio
2. you have to disable fw_getenv() function because
devicetree-enabled kernel will hangs if started from u-boot:
> --- a/arch/mips/fw/lib/cmdline.c
> +++ b/arch/mips/fw/lib/cmdline.c
> @@ -51,6 +51,8 @@ char *fw_getenv(char *envname)
> {
> char *result = NULL;
>
> + return result;
> +
3. configure linux kernel and build vmlinux*.bin linux kernel image
3.1 with devicetree support
$ make ARCH=mips tl-wr1043nd_defconfig
$ make ARCH=mips CROSS_COMPILE=<your cross compiler> vmlinux.bin qca/ar9132_tl_wr1043nd_v1.dtb
$ cat arch/mips/boot/vmlinux.bin \
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dtb \
> vmlinux_dtb.bin
3.2 without devicetree support
$ make ARCH=mips tl-wr1043nd-no-dt_defconfig
$ make ARCH=mips CROSS_COMPILE=<your cross compiler> vmlinux.bin
4. put the vmlinux_dtb.bin and vmlinux.bin into the root directory of your tftp-server
5. connect to u-boot console
6. use u-boot to download vmlinux_dtb.bin into RAM of your board and run it:
6.1 with devicetree support
uboot> setenv serverip 192.168.1.2; setenv ipaddr 192.168.1.22
uboot> tftpboot 0x80060000 vmlinux_dtb.bin; go 0x80060000
6.2 without devicetree support
uboot> setenv serverip 192.168.1.2; setenv ipaddr 192.168.1.22
uboot> tftpboot 0x80060000 vmlinux.bin; go 0x80060000
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/tl-wr1043nd-no-dt_defconfig | 100 ++++++++++++++++++++++++++
arch/mips/configs/tl-wr1043nd_defconfig | 98 +++++++++++++++++++++++++
2 files changed, 198 insertions(+)
diff --git a/arch/mips/configs/tl-wr1043nd-no-dt_defconfig b/arch/mips/configs/tl-wr1043nd-no-dt_defconfig
new file mode 100644
index 0000000..f316305b
--- /dev/null
+++ b/arch/mips/configs/tl-wr1043nd-no-dt_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ATH79=y
+CONFIG_ATH79_MACH_TL_WR1043ND=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="rootfs.mipsI.cpio"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_ATH79=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_PHY_ATH79_USB is not set
+CONFIG_PHY_SIMPLE_PDEV=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="init=/bin/sh machtype=TL-WR1043ND console=ttyS0,115200 root=/dev/ram"
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_CRC_ITU_T=y
diff --git a/arch/mips/configs/tl-wr1043nd_defconfig b/arch/mips/configs/tl-wr1043nd_defconfig
new file mode 100644
index 0000000..785379f
--- /dev/null
+++ b/arch/mips/configs/tl-wr1043nd_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ATH79=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="rootfs.mipsI.cpio"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_ATH79=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PHY_SIMPLE_PDEV=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="init=/bin/sh machtype=DTB console=ttyS0,115200 root=/dev/ram"
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_CRC_ITU_T=y
--
2.7.0
^ permalink raw reply related [flat|nested] 20+ messages in thread