* [PATCH 1/3] MIPS: Reserve nosave data for hibernation
@ 2016-03-06 3:50 Huacai Chen
2016-03-06 3:50 ` [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification Huacai Chen
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Huacai Chen @ 2016-03-06 3:50 UTC (permalink / raw)
To: Ralf Baechle
Cc: Aurelien Jarno, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen
After commit 92923ca3aacef63c92dc (mm: meminit: only set page reserved
in the memblock region), the MIPS hibernation is broken. Because pages
in nosave data section should be "reserved", but currently they aren't
set to "reserved" at initialization. This patch makes hibernation work
again.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/kernel/setup.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 5fdaf8b..6f68cdd 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -706,6 +706,9 @@ static void __init arch_mem_init(char **cmdline_p)
for_each_memblock(reserved, reg)
if (reg->size != 0)
reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+
+ reserve_bootmem_region(__pa_symbol(&__nosave_begin),
+ __pa_symbol(&__nosave_end)); /* Reserve for hibernation */
}
static void __init resource_init(void)
--
2.7.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification
2016-03-06 3:50 [PATCH 1/3] MIPS: Reserve nosave data for hibernation Huacai Chen
@ 2016-03-06 3:50 ` Huacai Chen
2016-03-06 12:18 ` Sergei Shtylyov
2016-03-06 3:50 ` [PATCH 3/3] MIPS: Loongson-3: Adjust irq dispatch to speedup processing Huacai Chen
2016-03-06 12:17 ` [PATCH 1/3] MIPS: Reserve nosave data for hibernation Sergei Shtylyov
2 siblings, 1 reply; 5+ messages in thread
From: Huacai Chen @ 2016-03-06 3:50 UTC (permalink / raw)
To: Ralf Baechle
Cc: Aurelien Jarno, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen
Commit d5ece1cb074b2c708 (Fix ld-version.sh to handle large 3rd version
part) modifies the ld version description. This causes a build error on
Loongson-3, so fix it.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/loongson64/Platform | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index 85d8089..0fce460 100644
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -31,7 +31,7 @@ cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
# can't easily be used safely within the kbuild framework.
#
ifeq ($(call cc-ifversion, -ge, 0409, y), y)
- ifeq ($(call ld-ifversion, -ge, 22500000, y), y)
+ ifeq ($(call ld-ifversion, -ge, 225000000, y), y)
cflags-$(CONFIG_CPU_LOONGSON3) += \
$(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
else
--
2.7.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] MIPS: Loongson-3: Adjust irq dispatch to speedup processing
2016-03-06 3:50 [PATCH 1/3] MIPS: Reserve nosave data for hibernation Huacai Chen
2016-03-06 3:50 ` [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification Huacai Chen
@ 2016-03-06 3:50 ` Huacai Chen
2016-03-06 12:17 ` [PATCH 1/3] MIPS: Reserve nosave data for hibernation Sergei Shtylyov
2 siblings, 0 replies; 5+ messages in thread
From: Huacai Chen @ 2016-03-06 3:50 UTC (permalink / raw)
To: Ralf Baechle
Cc: Aurelien Jarno, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen
This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs
handled in the same dispatching. This can speedup interrupt processing.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/loongson64/loongson-3/irq.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
index 0f75b6b..8e76490 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -24,19 +24,21 @@ static void ht_irqdispatch(void)
}
}
+#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
+
void mach_irq_dispatch(unsigned int pending)
{
if (pending & CAUSEF_IP7)
do_IRQ(LOONGSON_TIMER_IRQ);
#if defined(CONFIG_SMP)
- else if (pending & CAUSEF_IP6)
+ if (pending & CAUSEF_IP6)
loongson3_ipi_interrupt(NULL);
#endif
- else if (pending & CAUSEF_IP3)
+ if (pending & CAUSEF_IP3)
ht_irqdispatch();
- else if (pending & CAUSEF_IP2)
+ if (pending & CAUSEF_IP2)
do_IRQ(LOONGSON_UART_IRQ);
- else {
+ if (pending & UNUSED_IPS) {
pr_err("%s : spurious interrupt\n", __func__);
spurious_interrupt();
}
--
2.7.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/3] MIPS: Reserve nosave data for hibernation
2016-03-06 3:50 [PATCH 1/3] MIPS: Reserve nosave data for hibernation Huacai Chen
2016-03-06 3:50 ` [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification Huacai Chen
2016-03-06 3:50 ` [PATCH 3/3] MIPS: Loongson-3: Adjust irq dispatch to speedup processing Huacai Chen
@ 2016-03-06 12:17 ` Sergei Shtylyov
2 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2016-03-06 12:17 UTC (permalink / raw)
To: Huacai Chen, Ralf Baechle
Cc: Aurelien Jarno, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu
Hello.
On 3/6/2016 6:50 AM, Huacai Chen wrote:
> After commit 92923ca3aacef63c92dc (mm: meminit: only set page reserved
> in the memblock region), the MIPS hibernation is broken. Because pages
scripts/checkpatch.pl now enforces certain commit citing style, yours
doesn't quite match it...
> in nosave data section should be "reserved", but currently they aren't
> set to "reserved" at initialization. This patch makes hibernation work
> again.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-03-06 12:18 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2016-03-06 3:50 [PATCH 1/3] MIPS: Reserve nosave data for hibernation Huacai Chen
2016-03-06 3:50 ` [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification Huacai Chen
2016-03-06 12:18 ` Sergei Shtylyov
2016-03-06 3:50 ` [PATCH 3/3] MIPS: Loongson-3: Adjust irq dispatch to speedup processing Huacai Chen
2016-03-06 12:17 ` [PATCH 1/3] MIPS: Reserve nosave data for hibernation Sergei Shtylyov
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