Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Paul Boddie <paul@boddie.org.uk>]

On 2026-10-25 12:14, H. Nikolaus Schaller wrote:
>> Am 25.10.2026 um 12:06 schrieb Paul Boddie <paul@boddie.org.uk>:
>> 
>> From the X1600 Programming Manual:
>> 
>> "2.2 PRID of X1600-CPU
>> Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a 
>> read-only register being
>> used to identify implementation detail of each SOC's CPU. Please refer 
>> to the programming
>> manual of XBurst CPU for detail of the register. For X1600, its value 
>> is 0x00D0000"
> 
> This seems to be a typo as it has only 7 digits. I have read from the 
> chip:
> 
> PRID table (as known from Programming Manuals)
> jz4780 0x3ee1024f (confirmed 0x3ee1024f on CI20 board)
> x1000 0x2ed1024f  (unconfimed)
> x1600 0x00d00000  (confirmed 0x00d00000 on LX16 board)
> X1830 0x00d00100  (unconfirmed)
> X2000 0x00132000  (read out from LX20 board)
> X2600 0x001320xx  (confirmed 0x00132000 on LX26 board)

Better references might be these:

XBurst®1 CPU Core Programming Manual
Section 2.3.1.8 Processor ID-PRId(CP0 Register 15, Select 0)

XBurst®2 CPU Core Programming Manual
Section 3.3.1.7 Processor ID-PRId(CP0 Register 15, Select 0)

However, they suggest a format which does not seem consistent with that 
used by the XBurst 1 chips.

Paul