From: Paul Boddie <paul@boddie.org.uk>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>,
linux-mips@vger.kernel.org,
Discussions about the Letux Kernel <letux-kernel@openphoenux.org>,
Andreas Kemnade <akemnade@kernel.org>
Subject: Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600
Date: Sun, 25 Oct 2026 11:06:51 +0000 [thread overview]
Message-ID: <00f33012e2f754e4dec0ec17a76d4285@boddie.org.uk> (raw)
In-Reply-To: <alpine.DEB.2.21.2610250558190.42255@angie.orcam.me.uk>
On 2026-10-25 06:00, Maciej W. Rozycki wrote:
> On Sat, 24 Oct 2026, H. Nikolaus Schaller wrote:
>>
>> Well, XBURST is an MIPS CPU architecture and not a SoC. So there
>> should be no X1600 in
>> this macro name, especially if this ends up in a non-SoC-specific
>> arch/mips/include.
>
> Is there a documentation reference available for this value of PrID?
From the X1600 Programming Manual:
"2.2 PRID of X1600-CPU
Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a
read-only register being
used to identify implementation detail of each SOC's CPU. Please refer
to the programming
manual of XBurst CPU for detail of the register. For X1600, its value is
0x00D0000"
As previously noted, see:
https://github.com/Ingenic-community/datasheets/tree/main/X
Paul
next prev parent reply other threads:[~2026-10-25 11:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 20:42 [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600 Olivier Louvignes
2026-10-24 17:17 ` H. Nikolaus Schaller
2026-10-25 6:00 ` Maciej W. Rozycki
2026-10-25 11:06 ` Paul Boddie [this message]
2026-10-25 12:14 ` H. Nikolaus Schaller
2026-10-25 14:07 ` Paul Boddie
2026-10-28 12:52 ` Maciej W. Rozycki
2026-10-25 22:20 ` Paul Cercueil
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