[PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Olivier Louvignes]

The X1600 reports PRId 0x00d00000: company Ingenic D0, implementation 0,
which cpu_probe_ingenic() rejects with "Unknown Ingenic Processor ID!"
before any console exists. It is an XBurst1 core like the X1830's, which
shares the D0 company ID, so handle it the same way.

Tested on a HiBy R1 (X1600), which boots v7.3 with this.

Signed-off-by: Olivier Louvignes <olivier@mgcrea.io>
---
 arch/mips/include/asm/cpu.h  | 1 +
 arch/mips/kernel/cpu-probe.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0fd9f9bbd21f..ff7b63587daa 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -186,6 +186,7 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
+#define PRID_IMP_XBURST_X1600	0x0000	/* XBurst®1 in the X1600 (PRId 0x00d00000)	*/
 #define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
 #define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
 #define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 489612ed9d49..e3b547307c77 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1769,6 +1769,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 	switch (c->processor_id & PRID_IMP_MASK) {
 
 	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
+	case PRID_IMP_XBURST_X1600:
 	case PRID_IMP_XBURST_REV1:
 
 		/*

base-commit: bfe97f12a0a64c3682be21a02404238e3b91e945
-- 
2.39.5

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[H. Nikolaus Schaller]

Hi,

> Am 23.10.2026 um 22:42 schrieb Olivier Louvignes <olivier@mgcrea.io>:
> 
> The X1600 reports PRId 0x00d00000: company Ingenic D0, implementation 0,
> which cpu_probe_ingenic() rejects with "Unknown Ingenic Processor ID!"
> before any console exists. It is an XBurst1 core like the X1830's, which
> shares the D0 company ID, so handle it the same way.
> 
> Tested on a HiBy R1 (X1600), which boots v7.3 with this.
> 
> Signed-off-by: Olivier Louvignes <olivier@mgcrea.io>
> ---
> arch/mips/include/asm/cpu.h  | 1 +
> arch/mips/kernel/cpu-probe.c | 1 +
> 2 files changed, 2 insertions(+)
> 
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 0fd9f9bbd21f..ff7b63587daa 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -186,6 +186,7 @@
>  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
>  */
> 
> +#define PRID_IMP_XBURST_X1600 0x0000 /* XBurst®1 in the X1600 (PRId 0x00d00000) */

Well, XBURST is an MIPS CPU architecture and not a SoC. So there should be no X1600 in
this macro name, especially if this ends up in a non-SoC-specific arch/mips/include.

Basically this matches what we have added in our LetuxOS kernel, but not only for the X1600:

	https://github.com/goldelico/letux-kernel/commit/ee3e4e8baeb6d8

So please take our patch and amend it if you think it needs to and add a Co-developed-By:
Or if you can wait a little we can submit it.

> #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
> #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
> #define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
> diff --git a/arch/mips/kernel/cpu-probe.c b/
> index 489612ed9d49..e3b547307c77 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1769,6 +1769,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
> switch (c->processor_id & PRID_IMP_MASK) {
> 
> /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
> + case PRID_IMP_XBURST_X1600:
> case PRID_IMP_XBURST_REV1:

Here, we also add XBURST2_R2 and set the __cpu_name fields, agnostic of the
SoC name "X1600":

https://github.com/goldelico/letux-kernel/commit/b799b9a5e4d3e1

> 
> /*
> 
> base-commit: bfe97f12a0a64c3682be21a02404238e3b91e945
> -- 
> 2.39.5
> 
> 

BR and thanks, H. Nikolaus Schaller <hns@goldelico.com>

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Maciej W. Rozycki]

On Sat, 24 Oct 2026, H. Nikolaus Schaller wrote:

> > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> > index 0fd9f9bbd21f..ff7b63587daa 100644
> > --- a/arch/mips/include/asm/cpu.h
> > +++ b/arch/mips/include/asm/cpu.h
> > @@ -186,6 +186,7 @@
> >  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
> >  */
> > 
> > +#define PRID_IMP_XBURST_X1600 0x0000 /* XBurst®1 in the X1600 (PRId 0x00d00000) */
> 
> Well, XBURST is an MIPS CPU architecture and not a SoC. So there should be no X1600 in
> this macro name, especially if this ends up in a non-SoC-specific arch/mips/include.

 Is there a documentation reference available for this value of PrID?

  Maciej

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Paul Boddie]

On 2026-10-25 06:00, Maciej W. Rozycki wrote:
> On Sat, 24 Oct 2026, H. Nikolaus Schaller wrote:
>> 
>> Well, XBURST is an MIPS CPU architecture and not a SoC. So there 
>> should be no X1600 in
>> this macro name, especially if this ends up in a non-SoC-specific 
>> arch/mips/include.
> 
>  Is there a documentation reference available for this value of PrID?

 From the X1600 Programming Manual:

"2.2 PRID of X1600-CPU
Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a 
read-only register being
used to identify implementation detail of each SOC's CPU. Please refer 
to the programming
manual of XBurst CPU for detail of the register. For X1600, its value is 
0x00D0000"

As previously noted, see:

https://github.com/Ingenic-community/datasheets/tree/main/X

Paul

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[H. Nikolaus Schaller]

> Am 25.10.2026 um 12:06 schrieb Paul Boddie <paul@boddie.org.uk>:
> 
> On 2026-10-25 06:00, Maciej W. Rozycki wrote:
>> On Sat, 24 Oct 2026, H. Nikolaus Schaller wrote:
>>> Well, XBURST is an MIPS CPU architecture and not a SoC. So there should be no X1600 in
>>> this macro name, especially if this ends up in a non-SoC-specific arch/mips/include.
>> Is there a documentation reference available for this value of PrID?
> 
> From the X1600 Programming Manual:
> 
> "2.2 PRID of X1600-CPU
> Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a read-only register being
> used to identify implementation detail of each SOC's CPU. Please refer to the programming
> manual of XBurst CPU for detail of the register. For X1600, its value is 0x00D0000"

This seems to be a typo as it has only 7 digits. I have read from the chip: 

PRID table (as known from Programming Manuals)
jz4780 0x3ee1024f (confirmed 0x3ee1024f on CI20 board)
x1000 0x2ed1024f  (unconfimed)
x1600 0x00d00000  (confirmed 0x00d00000 on LX16 board)
X1830 0x00d00100  (unconfirmed)
X2000 0x00132000  (read out from LX20 board)
X2600 0x001320xx  (confirmed 0x00132000 on LX26 board)


> 
> As previously noted, see:
> 
> https://github.com/Ingenic-community/datasheets/tree/main/X
> 
> Paul

BR,
Nikolaus

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Paul Boddie]

On 2026-10-25 12:14, H. Nikolaus Schaller wrote:
>> Am 25.10.2026 um 12:06 schrieb Paul Boddie <paul@boddie.org.uk>:
>> 
>> From the X1600 Programming Manual:
>> 
>> "2.2 PRID of X1600-CPU
>> Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a 
>> read-only register being
>> used to identify implementation detail of each SOC's CPU. Please refer 
>> to the programming
>> manual of XBurst CPU for detail of the register. For X1600, its value 
>> is 0x00D0000"
> 
> This seems to be a typo as it has only 7 digits. I have read from the 
> chip:
> 
> PRID table (as known from Programming Manuals)
> jz4780 0x3ee1024f (confirmed 0x3ee1024f on CI20 board)
> x1000 0x2ed1024f  (unconfimed)
> x1600 0x00d00000  (confirmed 0x00d00000 on LX16 board)
> X1830 0x00d00100  (unconfirmed)
> X2000 0x00132000  (read out from LX20 board)
> X2600 0x001320xx  (confirmed 0x00132000 on LX26 board)

Better references might be these:

XBurst®1 CPU Core Programming Manual
Section 2.3.1.8 Processor ID-PRId(CP0 Register 15, Select 0)

XBurst®2 CPU Core Programming Manual
Section 3.3.1.7 Processor ID-PRId(CP0 Register 15, Select 0)

However, they suggest a format which does not seem consistent with that 
used by the XBurst 1 chips.

Paul

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Maciej W. Rozycki]

On Sun, 25 Oct 2026, Paul Boddie wrote:

> Better references might be these:
> 
> XBurst®1 CPU Core Programming Manual
> Section 2.3.1.8 Processor ID-PRId(CP0 Register 15, Select 0)
> 
> XBurst®2 CPU Core Programming Manual
> Section 3.3.1.7 Processor ID-PRId(CP0 Register 15, Select 0)
> 
> However, they suggest a format which does not seem consistent with that used
> by the XBurst 1 chips.

 Why not?  Quoting:

1) Generation(15~13): The number of the architecture design.
   0 - XBurst1;
   1 - XBurst2;
   others, reserved
2) uA(12~8): micro architecture version.
   please reference to SOC document.

-- so 0x00d00000 could possibly be PRID_IMP_XBURST_REV0 and other values 
in <asm/cpu.h> seem consistent with this definition as well.  Unless I'm 
missing something, since this is not my usual area of activity.  I note 
that _REV1 and _REV2 are swapped WRT their respective numeric values and I 
don't know what the origin of this arrangement is, but in principle that 
is not against the numbering scheme.

  Maciej

Re: [PATCH] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Paul Cercueil]

Hi Maciej,

Le dimanche 25 octobre 2026 à 06:00 +0000, Maciej W. Rozycki a écrit :
> On Sat, 24 Oct 2026, H. Nikolaus Schaller wrote:
> 
> > > diff --git a/arch/mips/include/asm/cpu.h
> > > b/arch/mips/include/asm/cpu.h
> > > index 0fd9f9bbd21f..ff7b63587daa 100644
> > > --- a/arch/mips/include/asm/cpu.h
> > > +++ b/arch/mips/include/asm/cpu.h
> > > @@ -186,6 +186,7 @@
> > >  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
> > >  */
> > > 
> > > +#define PRID_IMP_XBURST_X1600 0x0000 /* XBurst®1 in the X1600
> > > (PRId 0x00d00000) */
> > 
> > Well, XBURST is an MIPS CPU architecture and not a SoC. So there
> > should be no X1600 in
> > this macro name, especially if this ends up in a non-SoC-specific
> > arch/mips/include.
> 
>  Is there a documentation reference available for this value of PrID?

It's explicitly listed in the X1600's programming manual, yes.

Cheers,
-Paul