MTD drivers and byte/word mode

MTD drivers and byte/word mode

[Stephen Mose Aaskov]

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I´m working on a 2.4 port to a design with FLASH devices connected through a 16 bit bus.
The FLASH (AMD) is set to word mode.

I have quite a hard time trying to understand the FLASH geometry settings and calculations of the addresses used for CFI query etc.
It looks as if the adresses calculated by cfi_build_cmd_addr() is the double of what my FLASH chips are using.
eg. the CFI query is written to 0xaa where my chip in word mode expects the query command to be written to 0x55

Is there any direct support in the MTD driver for differentiating between word/byte mode ?

The buswidth is set to 16 bits (=2), and interleave to 1 (I have two chips sharing the bus, not in parallel)



Stephen Mose Aaskov
Engineer, R&D
2M ELECTRONIC A/S
Malervej 10, DK-2630 Taastrup
Denmark
Tel: +45 43300555  Fax: +45 43300567

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MTD drivers and byte/word mode

[Stephen Mose Aaskov]

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I´m working on a 2.4 port to a design with FLASH devices connected through a 16 bit bus.
The FLASH (AMD) is set to word mode.

I have quite a hard time trying to understand the FLASH geometry settings and calculations of the addresses used for CFI query etc.
It looks as if the adresses calculated by cfi_build_cmd_addr() is the double of what my FLASH chips are using.
eg. the CFI query is written to 0xaa where my chip in word mode expects the query command to be written to 0x55

Is there any direct support in the MTD driver for differentiating between word/byte mode ?

The buswidth is set to 16 bits (=2), and interleave to 1 (I have two chips sharing the bus, not in parallel)



Stephen Mose Aaskov
Engineer, R&D
2M ELECTRONIC A/S
Malervej 10, DK-2630 Taastrup
Denmark
Tel: +45 43300555  Fax: +45 43300567

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Re: MTD drivers and byte/word mode

[Jon Burgess]

> It looks as if the adresses calculated by
> cfi_build_cmd_addr() is the double of what my FLASH
> chips are using.
> eg. the CFI query is written to 0xaa where my chip
> in word mode expects the query command to be written
> to 0x55

We have just such a setup working in our product with a 16 bit AMD flash using
the CFI diver.

The 0xAA address as far as the programmer is concerned looks wrong, but the
flash chip is expecting addresses of 16bit data which are shifted 1 address line
from the address of 8 bit data. On our board the generic 8/16 bit bus address
lines are connected to the 16 bit flash as:
     Bus A0 -> Unused
     Bus A1 -> Flash A0,
     Bus A2 -> Flash A1
     etc,

When the CPU accesses addres 0xAA the flash will see 0x55.

     Jon