[PATCH 2.4] trivial secondary cache probe fix for R5000/NEVADA

[PATCH 2.4] trivial secondary cache probe fix for R5000/NEVADA

[Brian Murphy]

Hi Ralf,
despite the comment there are at least two more processors this 
probe is needed/works for.

Please apply.

/Brian

Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.3.2.37
diff -u -r1.3.2.37 c-r4k.c
--- arch/mips/mm/c-r4k.c	13 Apr 2003 00:10:30 -0000	1.3.2.37
+++ arch/mips/mm/c-r4k.c	13 Apr 2003 18:32:21 -0000
@@ -996,6 +996,8 @@
 	case CPU_R4400PC:
 	case CPU_R4400SC:
 	case CPU_R4400MC:
+	case CPU_R5000:
+	case CPU_NEVADA:
 		probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
 		sc_present = probe_scache_kseg1(config);
 		break;

Re: [PATCH 2.4] trivial secondary cache probe fix for R5000/NEVADA

[Ralf Baechle]

On Sun, Apr 13, 2003 at 08:41:47PM +0200, Brian Murphy wrote:

> despite the comment there are at least two more processors this 
> probe is needed/works for.

I don't think we want to use this frightening jewel for more than necessary.
On the R5000 the secondary cache can nicely be probed by looking at the
c0_config register.  c0_config.sc=0 indicates a second level cache is
present, setting the se bit in the same register enables it and the two
ss bits contain the size - doesn't that sound so much nicer than the
insane fragile stunt necessary for the R4000?

  Ralf