Re: [PATCH 3/3] MIPS: SMP: Properly stop secondary CPUs for restart

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Mon, Apr 06, 2026 at 02:59:55AM +0300, Rany Hany wrote:
> @@ -422,13 +425,66 @@ static void stop_this_cpu(void *dummy)
>  	set_cpu_online(smp_processor_id(), false);
>  	calculate_cpu_foreign_map();
>  	local_irq_disable();
> -	while (1);
> +
> +	if (mips_cm_present() && r4k_blast_dcache) {
> +		unsigned int core = cpu_core(&current_cpu_data);
> +
> +		if (atomic_dec_and_test(&core_stop_count[core])) {
> +			/* Flush data cache */
> +			r4k_blast_dcache();
> +			__sync();
> +
> +			if (mips_cm_revision() < CM_REV_CM3) {
> +				/* Restrict coherence to own core first */
> +				write_gcr_cl_coherence(1 << core);
> +				read_gcr_cl_coherence();
> +				__sync();
> +			}
> +
> +			/* Disable coherence */
> +			write_gcr_cl_coherence(0);
> +			read_gcr_cl_coherence();
> +
> +			/* Gate the core clock */
> +			if (mips_cpc_present())
> +				write_cpc_cl_cmd(CPC_Cx_CMD_CLOCKOFF);
> +		}
> +	}
> +
> +	if (cpu_has_mipsmt) {
> +		/* The last active VPE on the core will gate the core clock
> +		 * and all other remaining VPEs will halt this TC instead.
> +		 *
> +		 * Note that on systems without CPC, this will be the
> +		 * only way to shutdown the CPU.
> +		 */
> +		write_c0_tchalt(TCHALT_H);
> +		instruction_hazard();
> +	}
> +
> +	while (1)
> +		cpu_relax();
>  }

is this whole dance safe for _all_ SOCs with CM and MIPSMT ? if not,
this should be moved to a not so generic place...

Thomas.

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