* [PATCH 4/5] MIPS: Honor L2 bypass bit
@ 2010-09-07 4:03 Kevin Cernekee
2010-09-07 4:03 ` Kevin Cernekee
0 siblings, 1 reply; 2+ messages in thread
From: Kevin Cernekee @ 2010-09-07 4:03 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
therefore Linux should not attempt to use it.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..d072b25 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
+
+ /* bypass bit */
+ if (config2 & (1 << 12))
+ return 0;
+
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH 4/5] MIPS: Honor L2 bypass bit
2010-09-07 4:03 [PATCH 4/5] MIPS: Honor L2 bypass bit Kevin Cernekee
@ 2010-09-07 4:03 ` Kevin Cernekee
0 siblings, 0 replies; 2+ messages in thread
From: Kevin Cernekee @ 2010-09-07 4:03 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
therefore Linux should not attempt to use it.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..d072b25 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
+
+ /* bypass bit */
+ if (config2 & (1 << 12))
+ return 0;
+
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2010-09-07 4:03 ` Kevin Cernekee
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