* [PATCH]: Same cp0 regs are 64bits and other 32bit
@ 2003-03-27 2:53 Juan Quintela
0 siblings, 0 replies; only message in thread
From: Juan Quintela @ 2003-03-27 2:53 UTC (permalink / raw)
To: Ralf Baechle, mipslist
Hi
*some* cp0 regs are unsigned long, not unsigned int.
Later, Juan.
build/arch/mips/kernel/traps.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)
diff -puN build/arch/mips/kernel/traps.c~cp0_regs_are_unsigned_long build/arch/mips/kernel/traps.c
--- 24/build/arch/mips/kernel/traps.c~cp0_regs_are_unsigned_long 2003-03-25 22:35:22.000000000 +0100
+++ 24-quintela/build/arch/mips/kernel/traps.c 2003-03-25 22:36:59.000000000 +0100
@@ -788,9 +788,8 @@ asmlinkage void cache_parity_error(void)
unsigned int reg_val;
/* For the moment, report the problem and hang. */
- reg_val = read_c0_errorepc();
printk("Cache error exception:\n");
- printk("cp0_errorepc == %08x\n", read_c0_errorepc());
+ printk("cp0_errorepc == %08lx\n", read_c0_errorepc());
reg_val = read_c0_cacheerr();
printk("c0_cacheerr == %08x\n", reg_val);
@@ -809,10 +808,10 @@ asmlinkage void cache_parity_error(void)
#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
if (reg_val & (1<<22))
- printk("DErrAddr0: 0x%08x\n", read_c0_derraddr0());
+ printk("DErrAddr0: 0x%08lx\n", read_c0_derraddr0());
if (reg_val & (1<<23))
- printk("DErrAddr1: 0x%08x\n", read_c0_derraddr1());
+ printk("DErrAddr1: 0x%08lx\n", read_c0_derraddr1());
#endif
panic("Can't handle the cache error!");
_
--
In theory, practice and theory are the same, but in practice they
are different -- Larry McVoy
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2003-03-27 2:55 UTC | newest]
Thread overview: (only message) (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2003-03-27 2:53 [PATCH]: Same cp0 regs are 64bits and other 32bit Juan Quintela
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox