From: Juan Quintela <quintela@mandrakesoft.com>
To: Ralf Baechle <ralf@linux-mips.org>, mipslist <linux-mips@linux-mips.org>
Subject: [PATCH]: c-r4k.c 5/7 unduplicate declarations
Date: Fri, 28 Mar 2003 01:52:32 +0100 [thread overview]
Message-ID: <m2ptoc9usv.fsf@neno.mitica> (raw)
Hi
Lots of _flush_* functions are asigned the same value in the
case of only pcache or scache.
Later, Juan.
build/arch/mips/mm/c-r4k.c | 20 ++++++++------------
1 files changed, 8 insertions(+), 12 deletions(-)
diff -puN build/arch/mips/mm/c-r4k.c~c-r4k_unduplicate_repated_code build/arch/mips/mm/c-r4k.c
--- 24/build/arch/mips/mm/c-r4k.c~c-r4k_unduplicate_repated_code 2003-03-28 00:58:39.000000000 +0100
+++ 24-quintela/build/arch/mips/mm/c-r4k.c 2003-03-28 01:01:43.000000000 +0100
@@ -699,12 +699,7 @@ static void __init setup_noscache_funcs(
}
break;
}
- _flush_cache_all = r4k_flush_pcache_all;
___flush_cache_all = r4k_flush_pcache_all;
- _flush_cache_mm = r4k_flush_cache_mm;
- _flush_cache_page = r4k_flush_cache_page;
- _flush_icache_page = r4k_flush_icache_page;
- _flush_cache_range = r4k_flush_cache_range;
_dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
_dma_cache_wback = r4k_dma_cache_wback_inv_pc;
@@ -735,12 +730,7 @@ static void __init setup_scache_funcs(vo
break;
}
- _flush_cache_all = r4k_flush_pcache_all;
___flush_cache_all = r4k_flush_scache_all;
- _flush_cache_mm = r4k_flush_cache_mm;
- _flush_cache_range = r4k_flush_cache_range;
- _flush_cache_page = r4k_flush_cache_page;
- _flush_icache_page = r4k_flush_icache_page;
_dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
_dma_cache_wback = r4k_dma_cache_wback_inv_sc;
@@ -793,6 +783,14 @@ void __init ld_mmu_r4xx0(void)
probe_dcache(config);
setup_scache(config);
+ _flush_cache_all = r4k_flush_pcache_all;
+ _flush_cache_range = r4k_flush_cache_range;
+ _flush_icache_range = r4k_flush_icache_range; /* Ouch */
+ _flush_cache_mm = r4k_flush_cache_mm;
+ _flush_cache_page = r4k_flush_cache_page;
+ _flush_dcache_page = r4k_flush_dcache_page;
+ _flush_icache_page = r4k_flush_icache_page;
+
switch(mips_cpu.cputype) {
case CPU_R4600: /* QED style two way caches? */
case CPU_R4700:
@@ -801,7 +799,6 @@ void __init ld_mmu_r4xx0(void)
_flush_cache_page = r4k_flush_cache_page_r4600;
}
- _flush_dcache_page = r4k_flush_dcache_page;
switch(read_c0_prid() & 0xfff0) {
case 0x2010:
@@ -813,7 +810,6 @@ void __init ld_mmu_r4xx0(void)
default:
_flush_cache_sigtramp = r4k_flush_cache_sigtramp;
}
- _flush_icache_range = r4k_flush_icache_range; /* Ouch */
__flush_cache_all();
}
_
--
In theory, practice and theory are the same, but in practice they
are different -- Larry McVoy
reply other threads:[~2003-03-28 0:55 UTC|newest]
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