* Re: [PATCH] Fix IP32 breakage
From: Giuseppe Sacco @ 2008-01-06 21:44 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <20080106185852.GA5530@deprecation.cyrius.com>
I tested the original patch (2.6.24-rc6) and the system finally boot correctly. The second patch (related to meth) also works great on two different O2 systems.
On Sun, 6 Jan 2008 19:58:52 +0100 Martin Michlmayr <tbm@cyrius.com> wrote:
> The same patch is needed for 2.6.23. Here's a version that will apply
> against 2.6.23. Ralf, can you please commit that as well.
[...]
^ permalink raw reply
* Re: [PATCH] Fix IP32 breakage
From: Martin Michlmayr @ 2008-01-06 18:58 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips, ralf
In-Reply-To: <20080105111311.2DE1CC2EF8@solo.franken.de>
The same patch is needed for 2.6.23. Here's a version that will apply
against 2.6.23. Ralf, can you please commit that as well.
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer <tsbogend@alpha.franken.de> [2008-01-05 12:13]:
- suppress master aborts during config read
- set io_map_base
- only fixup end of iomem resource to avoid failing request_resource
in serial driver
- killed useless setting of crime_int bit, which caused wrong interrupts
- use physcial address for serial port platform device and let 8250
driver do the ioremap
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index fe54514..e958818 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -42,6 +42,10 @@ static int
mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
+ u32 control = mace->pci.control;
+
+ /* disable master aborts interrupts during config read */
+ mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
@@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
*val = mace->pci.config_data.l;
break;
}
+ /* ack possible master abort */
+ mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
+ mace->pci.control = control;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 618ea7d..532b561 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
+ .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
};
static int __init mace_init(void)
@@ -135,7 +136,8 @@ static int __init mace_init(void)
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
- iomem_resource = mace_pci_mem_resource;
+ /* extend memory resources */
+ iomem_resource.end = mace_pci_mem_resource.end;
ioport_resource = mace_pci_io_resource;
register_pci_controller(&mace_pci_controller);
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index fb9da9a..6eb982f 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -416,7 +416,6 @@ static void ip32_irq0(void)
crime_int = crime->istat & crime_mask;
irq = __ffs(crime_int);
- crime_int = 1 << irq;
if (crime_int & CRIME_MACEISA_INT_MASK) {
unsigned long mace_int = mace->perif.ctrl.istat;
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index 7309e48..89a71f4 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -13,21 +13,22 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
-/*
- * .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
- */
-#define MACE_PORT(int) \
+#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
+#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
+
+#define MACE_PORT(offset,_irq) \
{ \
- .irq = int, \
+ .mapbase = MACE_BASE + offset, \
+ .irq = _irq, \
.uartclk = 1843200, \
.iotype = UPIO_MEM, \
- .flags = UPF_SKIP_TEST, \
+ .flags = UPF_SKIP_TEST|UPF_IOREMAP, \
.regshift = 8, \
}
static struct plat_serial8250_port uart8250_data[] = {
- MACE_PORT(MACEISA_SERIAL1_IRQ),
- MACE_PORT(MACEISA_SERIAL2_IRQ),
+ MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
+ MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
{ },
};
@@ -41,9 +42,6 @@ static struct platform_device uart8250_device = {
static int __init uart8250_init(void)
{
- uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1;
- uart8250_data[1].membase = (void __iomem *) &mace->isa.serial1;
-
return platform_device_register(&uart8250_device);
}
--
Martin Michlmayr
http://www.cyrius.com/
^ permalink raw reply related
* Re: [PATCH] METH: fix MAC address handling
From: Thomas Bogendoerfer @ 2008-01-06 11:38 UTC (permalink / raw)
To: David Miller; +Cc: netdev, linux-mips, ralf, jgarzik
In-Reply-To: <20080106.002305.99653155.davem@davemloft.net>
On Sun, Jan 06, 2008 at 12:23:05AM -0800, David Miller wrote:
> > + u64 macaddr;
> >
> > - for (i = 0; i < 6; i++)
> > - dev->dev_addr[i] = o2meth_eaddr[i];
> > DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr));
> > - mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
> > + macaddr = 0;
> > + for (i = 0; i < 6; i++)
> > + macaddr |= dev->dev_addr[i] << ((5 - i) * 8);
> > +
> > + mace->eth.mac_addr = macaddr;
> > }
> >
> > /*
>
> Can you double-check that this conversion is equivalent.
yes, I did.
> I know that this whole driver is full of assumptions about
> the endianness of the system this chip is found on, so
> I'm only interested in if the transformation is equivalent
> and the driver will keep working properly.
I've tested the driver and it's still working :-)
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply
* Re: [PATCH] METH: fix MAC address handling
From: David Miller @ 2008-01-06 8:23 UTC (permalink / raw)
To: tsbogend; +Cc: netdev, linux-mips, ralf, jgarzik
In-Reply-To: <20080105224842.78EDCC2EFB@solo.franken.de>
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Sat, 5 Jan 2008 23:48:42 +0100 (CET)
> meth didn't set a valid mac address during probing, but later during
> open. Newer kernel refuse to open device with 00:00:00:00:00:00 as
> mac address -> dead ethernet. This patch sets the mac address in
> the probe function and uses only the mac address from the netdevice
> struct when setting up the hardware.
>
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Applied, thanks.
> + u64 macaddr;
>
> - for (i = 0; i < 6; i++)
> - dev->dev_addr[i] = o2meth_eaddr[i];
> DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr));
> - mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
> + macaddr = 0;
> + for (i = 0; i < 6; i++)
> + macaddr |= dev->dev_addr[i] << ((5 - i) * 8);
> +
> + mace->eth.mac_addr = macaddr;
> }
>
> /*
Can you double-check that this conversion is equivalent.
I know that this whole driver is full of assumptions about
the endianness of the system this chip is found on, so
I'm only interested in if the transformation is equivalent
and the driver will keep working properly.
Thanks.
^ permalink raw reply
* [PATCH] METH: fix MAC address handling
From: Thomas Bogendoerfer @ 2008-01-05 22:48 UTC (permalink / raw)
To: netdev, linux-mips; +Cc: ralf, jgarzik
meth didn't set a valid mac address during probing, but later during
open. Newer kernel refuse to open device with 00:00:00:00:00:00 as
mac address -> dead ethernet. This patch sets the mac address in
the probe function and uses only the mac address from the netdevice
struct when setting up the hardware.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
drivers/net/meth.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/meth.c b/drivers/net/meth.c
index 0c89b02..cdaa8fc 100644
--- a/drivers/net/meth.c
+++ b/drivers/net/meth.c
@@ -95,11 +95,14 @@ static inline void load_eaddr(struct net_device *dev)
{
int i;
DECLARE_MAC_BUF(mac);
+ u64 macaddr;
- for (i = 0; i < 6; i++)
- dev->dev_addr[i] = o2meth_eaddr[i];
DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr));
- mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
+ macaddr = 0;
+ for (i = 0; i < 6; i++)
+ macaddr |= dev->dev_addr[i] << ((5 - i) * 8);
+
+ mace->eth.mac_addr = macaddr;
}
/*
@@ -794,6 +797,7 @@ static int __init meth_probe(struct platform_device *pdev)
#endif
dev->irq = MACE_ETHERNET_IRQ;
dev->base_addr = (unsigned long)&mace->eth;
+ memcpy(dev->dev_addr, o2meth_eaddr, 6);
priv = netdev_priv(dev);
spin_lock_init(&priv->meth_lock);
^ permalink raw reply related
* Re: Arch/mips/kernel/vpe.c
From: Thiemo Seufer @ 2008-01-05 17:05 UTC (permalink / raw)
To: KokHow.Teh; +Cc: linux-mips
In-Reply-To: <31E09F73562D7A4D82119D7F6C1729860320EADA@sinse303.ap.infineon.com>
KokHow.Teh@infineon.com wrote:
> Hi;
> I am working on MIPS34KC with APRP kernel and I use uclibc
> gccc-3.4.4 to build applications to run on VPE1. The present
> implementation of VPE loader is limited to a few relocation types which
> are used when mips_sde compiler is used. However, the relocatable binary
> churn out from my uclibc-gcc-3.4.4 has more other relocation types than
> the ones defined in arch/mips/kernel/vpe.c, especially those with GOT
> relocation types. I have taken a look at the System V ABI Third Edition
> but if anybody has any code reference and pointers to how each
> relocation types should be implemented in C-code, it would be very
> helpful.
The most likely place to look at would be the binutils source code. That
said, you can probably get away without enhancing the VPE loader by using
a) fully linked (non-relocatable) executables, or
b) non-PIC code, like SDE does
Regardless of your choice, you will have to make sure the uclibc toolchain
doesn't use any libraries which need Linux facilities, as the bare-metal
environment on VPE1 doesn't provide them. For that reason I believe you
are better of with SDE or a similiar mips*-elf configured toolchain.
Thiemo
^ permalink raw reply
* Re: [MIPS] Fix modpost warning in raw binary builds.
From: Atsushi Nemoto @ 2008-01-05 15:48 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
In-Reply-To: <S20039888AbXJPTFk/20071016190540Z+81757@ftp.linux-mips.org>
On Tue, 16 Oct 2007 20:05:35 +0100, linux-mips@linux-mips.org wrote:
> Author: Ralf Baechle <ralf@linux-mips.org> Tue Oct 16 20:05:18 2007 +0100
> Commit: 017e3a492683b32d17dcd1b13b279745cc656073
> Gitweb: http://www.linux-mips.org/g/linux/017e3a49
> Branch: master
>
> MODPOST vmlinux.o
> WARNING: vmlinux.o(.text+0x478): Section mismatch: reference to .init.text:start_kernel (between '_stext' and 'run_init_process')
This commit should break CONFIG_BOOT_RAW. Since I do not have any
good idea to avoid this warning, reverting this commit would be the
best for now. The warning is just a false positive anyway.
---
Atsushi Nemoto
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Atsushi Nemoto @ 2008-01-05 15:07 UTC (permalink / raw)
To: gregor.waltz; +Cc: linux-mips
In-Reply-To: <477E7DAE.2080005@raritan.com>
On Fri, 04 Jan 2008 13:40:46 -0500, Gregor Waltz <gregor.waltz@raritan.com> wrote:
> sendRRQ vmlinux.bin
> load linux length 0x34408a
> Checking CRC on downloaded RAM image
> /
> CRC Check passed
> Image Started At Address 0x80020000.
> Image Length = 3424394 (0x34408a).
> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
Are you loading an ELF binary or a raw binary image? If your loader
does not handle ELF headers, you should do some trick to start running
your kernel at correct address.
If you were using 2.6.23, CONFIG_BOOT_RAW might help you.
But it seems CONFIG_BOOT_RAW is broken on current git again. It will
be an another story... :-<
---
Atsushi Nemoto
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Ralf Baechle @ 2008-01-05 14:45 UTC (permalink / raw)
To: Gregor Waltz; +Cc: linux-mips
In-Reply-To: <477E6296.7090605@raritan.com>
On Fri, Jan 04, 2008 at 11:45:10AM -0500, Gregor Waltz wrote:
> We want to update to a 2.6 kernel, recent build tools, and saner system
> libraries. Although, it seems that the JMR 3927 is still technically
> supported, I have not found any info on whether anybody is still running
> Linux on it and what combination of software they are using. Any idea?
> Is there a combination of software versions that are known to work on this
> hardware?
It's years since I last had a report of the JMR3927. Since that time
the code is maintained without the possibility of testing.
> I have used crosstool 0.43 to build:
> binutils 2.15
> gcc 3.4.5
> glibc 2.3.6
>
> I cannot get these kernels to build:
> linux-2.6.13
> linux-2.6.15
> linux-2.6.16.57
> linux-2.6.17.14
> linux-2.6.9
These themselves are rather old.
> My colleague and I have built these:
> linux-2.6.21.7
> linux-2.6.23.9
> linux-2.6.23.12
The build since we tried to fix the JMR3927 as good as possible without
having access to hardware. Which of course means almost certainly the
one or other buglet is left in the code ...
> However, they all yield a TLBL exception similar to the following:
>
> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
>
> Each build has different exception values. The values are the same each
> attempt with the same build.
... quod erat demonstrandum.
> Is this a problem in the kernel code or the build tools?
Well possible a bit of both ...
> Any ideas on how to make it run?
You may want to switch to a recent binutils like 2.18 and gcc 4.2.2.
There was a change related to linker scripts and I think that change
requires a recent binutils version.
> Using the recently built tools, I am currently trying to build the 2.4.12
> kernel that is known to work, which is proving difficult. If I can get it
> to build, I am hoping to see whether the tools are able to build a
> functioning kernel.
2.4.12 had various alergies against modern toolchains. So you may want
to retain a copy of your old toolchain for use with 2.4.12. later 2.4
versions have been fixed to build with recent toolchains.
Ralf
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Atsushi Nemoto @ 2008-01-05 14:42 UTC (permalink / raw)
To: gregor.waltz; +Cc: linux-mips
In-Reply-To: <477EB2EA.7060009@raritan.com>
On Fri, 04 Jan 2008 17:27:54 -0500, Gregor Waltz <gregor.waltz@raritan.com> wrote:
> Our 2.4.12 kernel uses -mcpu=r3000 -mips1 to build the kernel. I tried
> switching the arch to r3000 from r3900 in 2.6.23.9, but that did not
> help. Perhaps -mips1 or an equivalent could help? I will try on Monday.
I think both mcpu=r3000 and r3900 should work. But I believe at least
one kernel patch is required for all MIPS I platforms including JMR3927.
http://www.linux-mips.org/archives/linux-mips/2007-02/msg00320.html
---
Atsushi Nemoto
^ permalink raw reply
* Re: [PATCH] Assume newer R4000/R4400 don't have the mfc0 count bug
From: Ralf Baechle @ 2008-01-05 12:06 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips
In-Reply-To: <20080104223831.15FF4C2EF3@solo.franken.de>
On Fri, Jan 04, 2008 at 11:38:31PM +0100, Thomas Bogendoerfer wrote:
> Assume newer R4000/R4400 don't have the mfc0 count bug
Applied,
Ralf
^ permalink raw reply
* Re: [PATCH] Fix IP32 breakage
From: Ralf Baechle @ 2008-01-05 11:58 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips
In-Reply-To: <20080105111311.2DE1CC2EF8@solo.franken.de>
On Sat, Jan 05, 2008 at 12:13:11PM +0100, Thomas Bogendoerfer wrote:
> - suppress master aborts during config read
> - set io_map_base
> - only fixup end of iomem resource to avoid failing request_resource
> in serial driver
> - killed useless setting of crime_int bit, which caused wrong interrupts
> - use physcial address for serial port platform device and let 8250
> driver do the ioremap
>
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thanks, applied.
Ralf
^ permalink raw reply
* Arch/mips/kernel/vpe.c
From: KokHow.Teh @ 2008-01-05 11:29 UTC (permalink / raw)
To: linux-mips
Hi;
I am working on MIPS34KC with APRP kernel and I use uclibc
gccc-3.4.4 to build applications to run on VPE1. The present
implementation of VPE loader is limited to a few relocation types which
are used when mips_sde compiler is used. However, the relocatable binary
churn out from my uclibc-gcc-3.4.4 has more other relocation types than
the ones defined in arch/mips/kernel/vpe.c, especially those with GOT
relocation types. I have taken a look at the System V ABI Third Edition
but if anybody has any code reference and pointers to how each
relocation types should be implemented in C-code, it would be very
helpful.
Thanks.
Regards,
KH
^ permalink raw reply
* Arch/mips/kernel/vpe.c
From: KokHow.Teh @ 2008-01-05 11:29 UTC (permalink / raw)
To: linux-mips
Hi;
I am working on MIPS34KC with APRP kernel and I use uclibc
gccc-3.4.4 to build applications to run on VPE1. The present
implementation of VPE loader is limited to a few relocation types which
are used when mips_sde compiler is used. However, the relocatable binary
churn out from my uclibc-gcc-3.4.4 has more other relocation types than
the ones defined in arch/mips/kernel/vpe.c, especially those with GOT
relocation types. I have taken a look at the System V ABI Third Edition
but if anybody has any code reference and pointers to how each
relocation types should be implemented in C-code, it would be very
helpful.
Thanks.
Regards,
KH
^ permalink raw reply
* [PATCH] Fix IP32 breakage
From: Thomas Bogendoerfer @ 2008-01-05 11:13 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
- suppress master aborts during config read
- set io_map_base
- only fixup end of iomem resource to avoid failing request_resource
in serial driver
- killed useless setting of crime_int bit, which caused wrong interrupts
- use physcial address for serial port platform device and let 8250
driver do the ioremap
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/pci/ops-mace.c | 7 +++++++
arch/mips/pci/pci-ip32.c | 4 +++-
arch/mips/sgi-ip32/ip32-irq.c | 1 -
arch/mips/sgi-ip32/ip32-platform.c | 20 +++++++++-----------
4 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index fe54514..e958818 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -42,6 +42,10 @@ static int
mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
+ u32 control = mace->pci.control;
+
+ /* disable master aborts interrupts during config read */
+ mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
@@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
*val = mace->pci.config_data.l;
break;
}
+ /* ack possible master abort */
+ mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
+ mace->pci.control = control;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 618ea7d..532b561 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
+ .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
};
static int __init mace_init(void)
@@ -135,7 +136,8 @@ static int __init mace_init(void)
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
- iomem_resource = mace_pci_mem_resource;
+ /* extend memory resources */
+ iomem_resource.end = mace_pci_mem_resource.end;
ioport_resource = mace_pci_io_resource;
register_pci_controller(&mace_pci_controller);
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index cab7cc2..b0ea0e4 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -426,7 +426,6 @@ static void ip32_irq0(void)
crime_int = crime->istat & crime_mask;
irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
- crime_int = 1 << irq;
if (crime_int & CRIME_MACEISA_INT_MASK) {
unsigned long mace_int = mace->perif.ctrl.istat;
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index 77febd6..89a71f4 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -13,21 +13,22 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
-/*
- * .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
- */
-#define MACE_PORT(int) \
+#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
+#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
+
+#define MACE_PORT(offset,_irq) \
{ \
- .irq = int, \
+ .mapbase = MACE_BASE + offset, \
+ .irq = _irq, \
.uartclk = 1843200, \
.iotype = UPIO_MEM, \
- .flags = UPF_SKIP_TEST, \
+ .flags = UPF_SKIP_TEST|UPF_IOREMAP, \
.regshift = 8, \
}
static struct plat_serial8250_port uart8250_data[] = {
- MACE_PORT(MACEISA_SERIAL1_IRQ),
- MACE_PORT(MACEISA_SERIAL2_IRQ),
+ MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
+ MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
{ },
};
@@ -41,9 +42,6 @@ static struct platform_device uart8250_device = {
static int __init uart8250_init(void)
{
- uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1;
- uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2;
-
return platform_device_register(&uart8250_device);
}
^ permalink raw reply related
* [PATCH] Assume newer R4000/R4400 don't have the mfc0 count bug
From: Thomas Bogendoerfer @ 2008-01-04 22:38 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
Assume newer R4000/R4400 don't have the mfc0 count bug
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 1ecfbb7..2995be1 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -147,9 +147,9 @@ static __init int cpu_has_mfc0_count_bug(void)
return 1;
/*
- * I don't have erratas for newer R4400 so be paranoid.
+ * we assume newer revisions are ok
*/
- return 1;
+ return 0;
}
return 0;
^ permalink raw reply related
* [PATCH] SNI_RM: collected changes
From: Thomas Bogendoerfer @ 2008-01-04 22:31 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
- EISA support for non PCI RMs (RM200 and RM400-xxx). The major part
is the splitting of the EISA and onboard ISA of the RM200, which
makes the EISA bus on the RM200 look like on other RMs.
- 64bit kernel support
- system type detection is now common for big and little endian (thanks
Ralf)
- moved sniprom code to arch/mips/fw
- added call_o32 function to arch/mips/fw/lib, which uses a private
stack for calling prom functions
- fix problem with isa interrupts, which makes using pit clockevent
possible
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
This is 2.6.25 material and replaces [PATCH] SNI_RM: EISA support for
A20R/RM200
arch/mips/Kconfig | 4 +
arch/mips/Makefile | 2 +
arch/mips/fw/lib/Makefile | 5 +
arch/mips/fw/lib/call_o32.S | 97 +++++++++++++
arch/mips/fw/sni/Makefile | 5 +
arch/mips/fw/sni/sniprom.c | 152 ++++++++++++++++++++
arch/mips/sni/Makefile | 2 +-
arch/mips/sni/a20r.c | 13 ++-
arch/mips/sni/eisa.c | 52 +++++++
arch/mips/sni/irq.c | 4 +-
arch/mips/sni/rm200.c | 326 +++++++++++++++++++++++++++++++++++++++++--
arch/mips/sni/setup.c | 143 +++++++++++++++++++-
arch/mips/sni/sniprom.c | 251 ---------------------------------
arch/mips/sni/time.c | 1 +
include/asm-mips/bootinfo.h | 1 +
include/asm-mips/mipsprom.h | 2 +
include/asm-mips/sni.h | 159 ++++++++++++---------
18 files changed, 1042 insertions(+), 338 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 291d368..515fcac 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -573,6 +573,7 @@ config SNI_RM
bool "SNI RM200/300/400"
select ARC if CPU_LITTLE_ENDIAN
select ARC32 if CPU_LITTLE_ENDIAN
+ select SNIPROM if CPU_BIG_ENDIAN
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
@@ -957,6 +959,9 @@ config SERIAL_RM9000
config ARC32
bool
+config SNIPROM
+ bool
+
config BOOT_ELF32
bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a1f8d8b..f2ea18b 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -152,6 +152,8 @@ endif
#
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
+libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
+libs-y += arch/mips/fw/lib/
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
#
diff --git a/arch/mips/fw/lib/Makefile b/arch/mips/fw/lib/Makefile
new file mode 100644
index 0000000..84befc9
--- /dev/null
+++ b/arch/mips/fw/lib/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for generic prom monitor library routines under Linux.
+#
+
+lib-$(CONFIG_64BIT) += call_o32.o
diff --git a/arch/mips/fw/lib/call_o32.S b/arch/mips/fw/lib/call_o32.S
new file mode 100644
index 0000000..bdf7d1d
--- /dev/null
+++ b/arch/mips/fw/lib/call_o32.S
@@ -0,0 +1,97 @@
+/*
+ * arch/mips/dec/prom/call_o32.S
+ *
+ * O32 interface for the 64 (or N32) ABI.
+ *
+ * Copyright (C) 2002 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+/* Maximum number of arguments supported. Must be even! */
+#define O32_ARGC 32
+/* Number of static registers we save. */
+#define O32_STATC 11
+/* Frame size for static register */
+#define O32_FRAMESZ (SZREG * O32_STATC)
+/* Frame size on new stack */
+#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC)
+
+ .text
+
+/*
+ * O32 function call dispatcher, for interfacing 32-bit ROM routines.
+ *
+ * The standard 64 (N32) calling sequence is supported, with a0
+ * holding a function pointer, a1 a new stack pointer, a2-a7 -- its
+ * first six arguments and the stack -- remaining ones (up to O32_ARGC,
+ * including a2-a7). Static registers, gp and fp are preserved, v0 holds
+ * a result. This code relies on the called o32 function for sp and ra
+ * restoration and this dispatcher has to be placed in a KSEGx (or KUSEG)
+ * address space. Any pointers passed have to point to addresses within
+ * one of these spaces as well.
+ */
+NESTED(call_o32, O32_FRAMESZ, ra)
+ REG_SUBU sp,O32_FRAMESZ
+
+ REG_S ra,O32_FRAMESZ-1*SZREG(sp)
+ REG_S fp,O32_FRAMESZ-2*SZREG(sp)
+ REG_S gp,O32_FRAMESZ-3*SZREG(sp)
+ REG_S s7,O32_FRAMESZ-4*SZREG(sp)
+ REG_S s6,O32_FRAMESZ-5*SZREG(sp)
+ REG_S s5,O32_FRAMESZ-6*SZREG(sp)
+ REG_S s4,O32_FRAMESZ-7*SZREG(sp)
+ REG_S s3,O32_FRAMESZ-8*SZREG(sp)
+ REG_S s2,O32_FRAMESZ-9*SZREG(sp)
+ REG_S s1,O32_FRAMESZ-10*SZREG(sp)
+ REG_S s0,O32_FRAMESZ-11*SZREG(sp)
+
+ move jp,a0
+ REG_SUBU s0,a1,O32_FRAMESZ_NEW
+ REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0)
+
+ sll a0,a2,zero
+ sll a1,a3,zero
+ sll a2,a4,zero
+ sll a3,a5,zero
+ sw a6,0x10(s0)
+ sw a7,0x14(s0)
+
+ PTR_LA t0,O32_FRAMESZ(sp)
+ PTR_LA t1,0x18(s0)
+ li t2,O32_ARGC-6
+1:
+ lw t3,(t0)
+ REG_ADDU t0,SZREG
+ sw t3,(t1)
+ REG_SUBU t2,1
+ REG_ADDU t1,4
+ bnez t2,1b
+
+ move sp,s0
+
+ jalr jp
+
+ REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp)
+
+ REG_L s0,O32_FRAMESZ-11*SZREG(sp)
+ REG_L s1,O32_FRAMESZ-10*SZREG(sp)
+ REG_L s2,O32_FRAMESZ-9*SZREG(sp)
+ REG_L s3,O32_FRAMESZ-8*SZREG(sp)
+ REG_L s4,O32_FRAMESZ-7*SZREG(sp)
+ REG_L s5,O32_FRAMESZ-6*SZREG(sp)
+ REG_L s6,O32_FRAMESZ-5*SZREG(sp)
+ REG_L s7,O32_FRAMESZ-4*SZREG(sp)
+ REG_L gp,O32_FRAMESZ-3*SZREG(sp)
+ REG_L fp,O32_FRAMESZ-2*SZREG(sp)
+ REG_L ra,O32_FRAMESZ-1*SZREG(sp)
+
+ REG_ADDU sp,O32_FRAMESZ
+ jr ra
+END(call_o32)
diff --git a/arch/mips/fw/sni/Makefile b/arch/mips/fw/sni/Makefile
new file mode 100644
index 0000000..d9740a3
--- /dev/null
+++ b/arch/mips/fw/sni/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the SNI prom monitor routines under Linux.
+#
+
+lib-$(CONFIG_SNIPROM) += sniprom.o
diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c
new file mode 100644
index 0000000..aec5dc0
--- /dev/null
+++ b/arch/mips/fw/sni/sniprom.c
@@ -0,0 +1,152 @@
+/*
+ * Big Endian PROM code for SNI RM machines
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
+ * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/console.h>
+
+#include <asm/addrspace.h>
+#include <asm/sni.h>
+#include <asm/mipsprom.h>
+#include <asm/mipsregs.h>
+#include <asm/bootinfo.h>
+
+/* special SNI prom calls */
+/*
+ * This does not exist in all proms - SINIX compares
+ * the prom env variable "version" against "2.0008"
+ * or greater. If lesser it tries to probe interesting
+ * registers
+ */
+#define PROM_GET_MEMCONF 58
+#define PROM_GET_HWCONF 61
+
+#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
+#define PROM_ENTRY(x) (PROM_VEC + (x))
+
+#define ___prom_putchar ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR))
+#define ___prom_getenv ((char *(*)(char *))PROM_ENTRY(PROM_GETENV))
+#define ___prom_get_memconf ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF))
+#define ___prom_get_hwconf ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF))
+
+#ifdef CONFIG_64BIT
+
+static u8 o32_stk[16384];
+#define O32_STK &o32_stk[sizeof(o32_stk)]
+
+#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
+ __asm__(#fun " = call_o32")
+
+int __PROM_O32(__prom_putchar, (int *(*)(int), void *, int));
+char *__PROM_O32(__prom_getenv, (char *(*)(char *), void *, char *));
+void __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *));
+u32 __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *));
+
+#define _prom_putchar(x) __prom_putchar(___prom_putchar, O32_STK, x)
+#define _prom_getenv(x) __prom_getenv(___prom_getenv, O32_STK, x)
+#define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x)
+#define _prom_get_hwconf() __prom_get_hwconf(___prom_get_hwconf, O32_STK)
+
+#else
+#define _prom_putchar(x) ___prom_putchar(x)
+#define _prom_getenv(x) ___prom_getenv(x)
+#define _prom_get_memconf(x) ___prom_get_memconf(x)
+#define _prom_get_hwconf(x) ___prom_get_hwconf(x)
+#endif
+
+void prom_putchar(char c)
+{
+ _prom_putchar(c);
+}
+
+
+char *prom_getenv(char *s)
+{
+ return _prom_getenv(s);
+}
+
+void *prom_get_hwconf(void)
+{
+ u32 hwconf = _prom_get_hwconf();
+
+ if (hwconf == 0xffffffff)
+ return NULL;
+
+ return (void *)CKSEG1ADDR(hwconf);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+/*
+ * /proc/cpuinfo system type
+ *
+ */
+char *system_type = "Unknown";
+const char *get_system_type(void)
+{
+ return system_type;
+}
+
+static void __init sni_mem_init(void)
+{
+ int i, memsize;
+ struct membank {
+ u32 size;
+ u32 base;
+ u32 size2;
+ u32 pad1;
+ u32 pad2;
+ } memconf[8];
+ int brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
+
+
+ /* MemSIZE from prom in 16MByte chunks */
+ memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
+
+ pr_debug("IDProm memsize: %u MByte\n", memsize);
+
+ /* get memory bank layout from prom */
+ _prom_get_memconf(&memconf);
+
+ pr_debug("prom_get_mem_conf memory configuration:\n");
+ for (i = 0; i < 8 && memconf[i].size; i++) {
+ if (brd_type == SNI_BRD_PCI_TOWER ||
+ brd_type == SNI_BRD_PCI_TOWER_CPLUS) {
+ if (memconf[i].base >= 0x20000000 &&
+ memconf[i].base < 0x30000000)
+ memconf[i].base -= 0x20000000;
+ }
+ pr_debug("Bank%d: %08x @ %08x\n", i,
+ memconf[i].size, memconf[i].base);
+ add_memory_region(memconf[i].base, memconf[i].size,
+ BOOT_MEM_RAM);
+ }
+}
+
+void __init prom_init(void)
+{
+ int argc = fw_arg0;
+ u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
+ int i;
+
+ sni_mem_init();
+
+ /* copy prom cmdline parameters to kernel cmdline */
+ for (i = 1; i < argc; i++) {
+ strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
+ if (i < (argc - 1))
+ strcat(arcs_cmdline, " ");
+ }
+}
+
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index 3a99cd6..a7dbeeb 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -3,6 +3,6 @@
#
obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
-obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
+obj-$(CONFIG_EISA) += eisa.o
EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index b746075..3f8cf5e 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -117,10 +117,19 @@ static struct resource sc26xx_rsrc[] = {
}
};
+static unsigned int sc26xx_data[2] = {
+ /* DTR | RTS | DSR | CTS | DCD | RI */
+ (8 << 0) | (4 << 4) | (6 << 8) | (0 << 12) | (6 << 16) | (0 << 20),
+ (3 << 0) | (2 << 4) | (1 << 8) | (2 << 12) | (3 << 16) | (4 << 20)
+};
+
static struct platform_device sc26xx_pdev = {
.name = "SC26xx",
.num_resources = ARRAY_SIZE(sc26xx_rsrc),
- .resource = sc26xx_rsrc
+ .resource = sc26xx_rsrc,
+ .dev = {
+ .platform_data = sc26xx_data,
+ }
};
static u32 a20r_ack_hwint(void)
@@ -231,9 +240,9 @@ static int __init snirm_a20r_setup_devinit(void)
platform_device_register(&sc26xx_pdev);
platform_device_register(&a20r_serial8250_device);
platform_device_register(&a20r_ds1216_device);
+ sni_eisa_root_init();
break;
}
-
return 0;
}
diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
new file mode 100644
index 0000000..2fd2412
--- /dev/null
+++ b/arch/mips/sni/eisa.c
@@ -0,0 +1,52 @@
+/*
+ * Virtual EISA root driver.
+ * Acts as a placeholder if we don't have a proper EISA bridge.
+ *
+ * (C) 2003 Marc Zyngier <maz@wild-wind.fr.eu.org>
+ * modified for SNI usage by Thomas Bogendoerfer
+ *
+ * This code is released under the GPL version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/eisa.h>
+#include <linux/init.h>
+
+/* The default EISA device parent (virtual root device).
+ * Now use a platform device, since that's the obvious choice. */
+
+static struct platform_device eisa_root_dev = {
+ .name = "eisa",
+ .id = 0,
+};
+
+static struct eisa_root_device eisa_bus_root = {
+ .dev = &eisa_root_dev.dev,
+ .bus_base_addr = 0,
+ .res = &ioport_resource,
+ .slots = EISA_MAX_SLOTS,
+ .dma_mask = 0xffffffff,
+ .force_probe = 1,
+};
+
+int __init sni_eisa_root_init(void)
+{
+ int r;
+
+ r = platform_device_register(&eisa_root_dev);
+ if (!r)
+ return r;
+
+ eisa_root_dev.dev.driver_data = &eisa_bus_root;
+
+ if (eisa_root_register(&eisa_bus_root)) {
+ /* A real bridge may have been registered before
+ * us. So quietly unregister. */
+ platform_device_unregister(&eisa_root_dev);
+ return -1;
+ }
+ return 0;
+}
+
+
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 9ccffdf..e8e72bb 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -35,14 +35,14 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
if (unlikely(irq < 0))
return IRQ_NONE;
- do_IRQ(irq);
+ generic_handle_irq(irq);
return IRQ_HANDLED;
}
struct irqaction sni_isa_irq = {
.handler = sni_isa_irq_handler,
.name = "ISA",
- .flags = IRQF_SHARED
+ .flags = IRQF_SHARED | IRQF_DISABLED
};
/*
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 67b061e..5310aa7 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -5,30 +5,36 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ *
+ * i8259 parts ripped out of arch/mips/kernel/i8259.c
*/
+#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
+#include <linux/io.h>
#include <asm/sni.h>
#include <asm/time.h>
#include <asm/irq_cpu.h>
-#define PORT(_base,_irq) \
+#define RM200_I8259A_IRQ_BASE 32
+
+#define MEMPORT(_base,_irq) \
{ \
- .iobase = _base, \
+ .mapbase = _base, \
.irq = _irq, \
.uartclk = 1843200, \
- .iotype = UPIO_PORT, \
- .flags = UPF_BOOT_AUTOCONF, \
+ .iotype = UPIO_MEM, \
+ .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \
}
static struct plat_serial8250_port rm200_data[] = {
- PORT(0x3f8, 4),
- PORT(0x2f8, 3),
+ MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
+ MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
{ },
};
@@ -112,15 +118,311 @@ static int __init snirm_setup_devinit(void)
platform_device_register(&rm200_ds1216_device);
platform_device_register(&snirm_82596_rm200_pdev);
platform_device_register(&snirm_53c710_rm200_pdev);
+ sni_eisa_root_init();
}
return 0;
}
device_initcall(snirm_setup_devinit);
+/*
+ * RM200 has an ISA and an EISA bus. The iSA bus is only used
+ * for onboard devices and also has twi i8259 PICs. Since these
+ * PICs are no accessible via inb/outb the following code uses
+ * readb/writeb to access them
+ */
+
+DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
+#define PIC_CMD 0x00
+#define PIC_IMR 0x01
+#define PIC_ISR PIC_CMD
+#define PIC_POLL PIC_ISR
+#define PIC_OCW3 PIC_ISR
+
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR 2
+#define MASTER_ICW4_DEFAULT 0x01
+#define SLAVE_ICW4_DEFAULT 0x01
+
+/*
+ * This contains the irq mask for both 8259A irq controllers,
+ */
+static unsigned int rm200_cached_irq_mask = 0xffff;
+static __iomem u8 *rm200_pic_master;
+static __iomem u8 *rm200_pic_slave;
+
+#define cached_master_mask (rm200_cached_irq_mask)
+#define cached_slave_mask (rm200_cached_irq_mask >> 8)
+
+static void sni_rm200_disable_8259A_irq(unsigned int irq)
+{
+ unsigned int mask;
+ unsigned long flags;
+
+ irq -= RM200_I8259A_IRQ_BASE;
+ mask = 1 << irq;
+ spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ rm200_cached_irq_mask |= mask;
+ if (irq & 8)
+ writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
+ else
+ writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
+ spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+}
+
+static void sni_rm200_enable_8259A_irq(unsigned int irq)
+{
+ unsigned int mask;
+ unsigned long flags;
+
+ irq -= RM200_I8259A_IRQ_BASE;
+ mask = ~(1 << irq);
+ spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ rm200_cached_irq_mask &= mask;
+ if (irq & 8)
+ writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
+ else
+ writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
+ spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+}
+
+static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
+{
+ int value;
+ int irqmask = 1 << irq;
+
+ if (irq < 8) {
+ writeb(0x0B, rm200_pic_master + PIC_CMD);
+ value = readb(rm200_pic_master + PIC_CMD) & irqmask;
+ writeb(0x0A, rm200_pic_master + PIC_CMD);
+ return value;
+ }
+ writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
+ value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);
+ writeb(0x0A, rm200_pic_slave + PIC_CMD);
+ return value;
+}
+
+/*
+ * Careful! The 8259A is a fragile beast, it pretty
+ * much _has_ to be done exactly like this (mask it
+ * first, _then_ send the EOI, and the order of EOI
+ * to the two 8259s is important!
+ */
+void sni_rm200_mask_and_ack_8259A(unsigned int irq)
+{
+ unsigned int irqmask;
+ unsigned long flags;
+
+ irq -= RM200_I8259A_IRQ_BASE;
+ irqmask = 1 << irq;
+ spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ /*
+ * Lightweight spurious IRQ detection. We do not want
+ * to overdo spurious IRQ handling - it's usually a sign
+ * of hardware problems, so we only do the checks we can
+ * do without slowing down good hardware unnecessarily.
+ *
+ * Note that IRQ7 and IRQ15 (the two spurious IRQs
+ * usually resulting from the 8259A-1|2 PICs) occur
+ * even if the IRQ is masked in the 8259A. Thus we
+ * can check spurious 8259A IRQs without doing the
+ * quite slow i8259A_irq_real() call for every IRQ.
+ * This does not cover 100% of spurious interrupts,
+ * but should be enough to warn the user that there
+ * is something bad going on ...
+ */
+ if (rm200_cached_irq_mask & irqmask)
+ goto spurious_8259A_irq;
+ rm200_cached_irq_mask |= irqmask;
+
+handle_real_irq:
+ if (irq & 8) {
+ readb(rm200_pic_slave + PIC_IMR);
+ writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
+ writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
+ writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
+ } else {
+ readb(rm200_pic_master + PIC_IMR);
+ writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
+ writeb(0x60+irq, rm200_pic_master + PIC_CMD);
+ }
+ spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+ return;
+
+spurious_8259A_irq:
+ /*
+ * this is the slow path - should happen rarely.
+ */
+ if (sni_rm200_i8259A_irq_real(irq))
+ /*
+ * oops, the IRQ _is_ in service according to the
+ * 8259A - not spurious, go handle it.
+ */
+ goto handle_real_irq;
+
+ {
+ static int spurious_irq_mask;
+ /*
+ * At this point we can be sure the IRQ is spurious,
+ * lets ACK and report it. [once per IRQ]
+ */
+ if (!(spurious_irq_mask & irqmask)) {
+ printk(KERN_DEBUG
+ "spurious RM200 8259A interrupt: IRQ%d.\n", irq);
+ spurious_irq_mask |= irqmask;
+ }
+ atomic_inc(&irq_err_count);
+ /*
+ * Theoretically we do not have to handle this IRQ,
+ * but in Linux this does not cause problems and is
+ * simpler for us.
+ */
+ goto handle_real_irq;
+ }
+}
+
+static struct irq_chip sni_rm200_i8259A_chip = {
+ .name = "RM200-XT-PIC",
+ .mask = sni_rm200_disable_8259A_irq,
+ .unmask = sni_rm200_enable_8259A_irq,
+ .mask_ack = sni_rm200_mask_and_ack_8259A,
+};
+
+/*
+ * Do the traditional i8259 interrupt polling thing. This is for the few
+ * cases where no better interrupt acknowledge method is available and we
+ * absolutely must touch the i8259.
+ */
+static inline int sni_rm200_i8259_irq(void)
+{
+ int irq;
+
+ spin_lock(&sni_rm200_i8259A_lock);
+
+ /* Perform an interrupt acknowledge cycle on controller 1. */
+ writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
+ irq = readb(rm200_pic_master + PIC_CMD) & 7;
+ if (irq == PIC_CASCADE_IR) {
+ /*
+ * Interrupt is cascaded so perform interrupt
+ * acknowledge on controller 2.
+ */
+ writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
+ irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;
+ }
+
+ if (unlikely(irq == 7)) {
+ /*
+ * This may be a spurious interrupt.
+ *
+ * Read the interrupt status register (ISR). If the most
+ * significant bit is not set then there is no valid
+ * interrupt.
+ */
+ writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */
+ if (~readb(rm200_pic_master + PIC_ISR) & 0x80)
+ irq = -1;
+ }
+
+ spin_unlock(&sni_rm200_i8259A_lock);
+
+ return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
+}
+
+void sni_rm200_init_8259A(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+
+ writeb(0xff, rm200_pic_master + PIC_IMR);
+ writeb(0xff, rm200_pic_slave + PIC_IMR);
+
+ writeb(0x11, rm200_pic_master + PIC_CMD);
+ writeb(0, rm200_pic_master + PIC_IMR);
+ writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
+ writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
+ writeb(0x11, rm200_pic_slave + PIC_CMD);
+ writeb(8, rm200_pic_slave + PIC_IMR);
+ writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
+ writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
+ udelay(100); /* wait for 8259A to initialize */
+
+ writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
+ writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
+
+ spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+}
+
+/*
+ * IRQ2 is cascade interrupt to second interrupt controller
+ */
+static struct irqaction sni_rm200_irq2 = {
+ no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
+};
+
+static struct resource sni_rm200_pic1_resource = {
+ .name = "onboard ISA pic1",
+ .start = 0x16000020,
+ .end = 0x16000023,
+ .flags = IORESOURCE_BUSY
+};
+
+static struct resource sni_rm200_pic2_resource = {
+ .name = "onboard ISA pic2",
+ .start = 0x160000a0,
+ .end = 0x160000a3,
+ .flags = IORESOURCE_BUSY
+};
+
+/* ISA irq handler */
+static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p)
+{
+ int irq;
+
+ irq = sni_rm200_i8259_irq();
+ if (unlikely(irq < 0))
+ return IRQ_NONE;
+
+ do_IRQ(irq);
+ return IRQ_HANDLED;
+}
+
+struct irqaction sni_rm200_i8259A_irq = {
+ .handler = sni_rm200_i8259A_irq_handler,
+ .name = "onboard ISA",
+ .flags = IRQF_SHARED
+};
+
+void __init sni_rm200_i8259_irqs(void)
+{
+ int i;
+
+ rm200_pic_master = ioremap_nocache(0x16000020, 4);
+ if (!rm200_pic_master)
+ return;
+ rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
+ if (!rm200_pic_master) {
+ iounmap(rm200_pic_master);
+ return;
+ }
+
+ insert_resource(&iomem_resource, &sni_rm200_pic1_resource);
+ insert_resource(&iomem_resource, &sni_rm200_pic2_resource);
+
+ sni_rm200_init_8259A();
+
+ for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
+ set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
+ handle_level_irq);
+
+ setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
+}
+
-#define SNI_RM200_INT_STAT_REG 0xbc000000
-#define SNI_RM200_INT_ENA_REG 0xbc080000
+#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
+#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)
#define SNI_RM200_INT_START 24
#define SNI_RM200_INT_END 28
@@ -181,17 +483,17 @@ void __init sni_rm200_irq_init(void)
* (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f;
+ sni_rm200_i8259_irqs();
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
set_irq_chip(i, &rm200_irq_type);
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
- setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
+ setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
+ setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq);
}
void __init sni_rm200_init(void)
{
- set_io_port_base(SNI_PORT_BASE + 0x02000000);
- ioport_resource.end += 0x02000000;
}
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index e8b26bd..5484e1c 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -19,11 +19,17 @@
#include <asm/sgialib.h>
#endif
+#ifdef CONFIG_SNIPROM
+#include <asm/mipsprom.h>
+#endif
+
+#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/sni.h>
unsigned int sni_brd_type;
+EXPORT_SYMBOL(sni_brd_type);
extern void sni_machine_restart(char *command);
extern void sni_machine_power_off(void);
@@ -47,20 +53,152 @@ static void __init sni_display_setup(void)
#endif
}
+static void __init sni_console_setup(void)
+{
+#ifndef CONFIG_ARC
+ char *ctype;
+ char *cdev;
+ char *baud;
+ int port;
+ static char options[8];
+
+ cdev = prom_getenv("console_dev");
+ if (strncmp(cdev, "tty", 3) == 0) {
+ ctype = prom_getenv("console");
+ switch (*ctype) {
+ default:
+ case 'l':
+ port = 0;
+ baud = prom_getenv("lbaud");
+ break;
+ case 'r':
+ port = 1;
+ baud = prom_getenv("rbaud");
+ break;
+ }
+ if (baud)
+ strcpy(options, baud);
+ if (strncmp(cdev, "tty552", 6) == 0)
+ add_preferred_console("ttyS", port,
+ baud ? options : NULL);
+ else
+ add_preferred_console("ttySC", port,
+ baud ? options : NULL);
+ }
+#endif
+}
+
+#ifdef DEBUG
+static void __init sni_idprom_dump(void)
+{
+ int i;
+
+ pr_debug("SNI IDProm dump:\n");
+ for (i = 0; i < 256; i++) {
+ if (i%16 == 0)
+ pr_debug("%04x ", i);
+
+ printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i));
+
+ if (i % 16 == 15)
+ printk("\n");
+ }
+}
+#endif
void __init plat_mem_setup(void)
{
+ int cputype;
+
set_io_port_base(SNI_PORT_BASE);
// ioport_resource.end = sni_io_resource.end;
/*
* Setup (E)ISA I/O memory access stuff
*/
- isa_slot_offset = 0xb0000000;
+ isa_slot_offset = CKSEG1ADDR(0xb0000000);
#ifdef CONFIG_EISA
EISA_bus = 1;
#endif
+ sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
+ cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE;
+ switch (sni_brd_type) {
+ case SNI_BRD_TOWER_OASIC:
+ switch (cputype) {
+ case SNI_CPU_M8030:
+ system_type = "RM400-330";
+ break;
+ case SNI_CPU_M8031:
+ system_type = "RM400-430";
+ break;
+ case SNI_CPU_M8037:
+ system_type = "RM400-530";
+ break;
+ case SNI_CPU_M8034:
+ system_type = "RM400-730";
+ break;
+ default:
+ system_type = "RM400-xxx";
+ break;
+ }
+ break;
+ case SNI_BRD_MINITOWER:
+ switch (cputype) {
+ case SNI_CPU_M8021:
+ case SNI_CPU_M8043:
+ system_type = "RM400-120";
+ break;
+ case SNI_CPU_M8040:
+ system_type = "RM400-220";
+ break;
+ case SNI_CPU_M8053:
+ system_type = "RM400-225";
+ break;
+ case SNI_CPU_M8050:
+ system_type = "RM400-420";
+ break;
+ default:
+ system_type = "RM400-xxx";
+ break;
+ }
+ break;
+ case SNI_BRD_PCI_TOWER:
+ system_type = "RM400-Cxx";
+ break;
+ case SNI_BRD_RM200:
+ system_type = "RM200-xxx";
+ break;
+ case SNI_BRD_PCI_MTOWER:
+ system_type = "RM300-Cxx";
+ break;
+ case SNI_BRD_PCI_DESKTOP:
+ switch (read_c0_prid() & 0xff00) {
+ case PRID_IMP_R4600:
+ case PRID_IMP_R4700:
+ system_type = "RM200-C20";
+ break;
+ case PRID_IMP_R5000:
+ system_type = "RM200-C40";
+ break;
+ default:
+ system_type = "RM200-Cxx";
+ break;
+ }
+ break;
+ case SNI_BRD_PCI_TOWER_CPLUS:
+ system_type = "RM400-Exx";
+ break;
+ case SNI_BRD_PCI_MTOWER_CPLUS:
+ system_type = "RM300-Exx";
+ break;
+ }
+ pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, system_type);
+
+#ifdef DEBUG
+ sni_idprom_dump();
+#endif
+
switch (sni_brd_type) {
case SNI_BRD_10:
case SNI_BRD_10NEW:
@@ -89,9 +227,10 @@ void __init plat_mem_setup(void)
pm_power_off = sni_machine_power_off;
sni_display_setup();
+ sni_console_setup();
}
-#if CONFIG_PCI
+#ifdef CONFIG_PCI
#include <linux/pci.h>
#include <video/vga.h>
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
deleted file mode 100644
index eff4b89..0000000
--- a/arch/mips/sni/sniprom.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Big Endian PROM code for SNI RM machines
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
- * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
- */
-
-#define DEBUG
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/console.h>
-
-#include <asm/addrspace.h>
-#include <asm/sni.h>
-#include <asm/mipsprom.h>
-#include <asm/mipsregs.h>
-#include <asm/bootinfo.h>
-
-/* special SNI prom calls */
-/*
- * This does not exist in all proms - SINIX compares
- * the prom env variable "version" against "2.0008"
- * or greater. If lesser it tries to probe interesting
- * registers
- */
-#define PROM_GET_MEMCONF 58
-
-#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
-#define PROM_ENTRY(x) (PROM_VEC + (x))
-
-
-static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR);
-
-void prom_putchar(char c)
-{
- __prom_putchar(c);
-}
-
-static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
-static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
-
-char *prom_getenv(char *s)
-{
- return __prom_getenv(s);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-/*
- * /proc/cpuinfo system type
- *
- */
-static const char *systype = "Unknown";
-const char *get_system_type(void)
-{
- return systype;
-}
-
-#define SNI_IDPROM_BASE 0xbff00000
-#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE+0x28) /* Memsize in 16MB quantities */
-#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE+0x29) /* Board Type */
-#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE+0x30) /* CPU Type */
-
-#define SNI_IDPROM_SIZE 0x1000
-
-#ifdef DEBUG
-static void __init sni_idprom_dump(void)
-{
- int i;
-
- pr_debug("SNI IDProm dump:\n");
- for (i = 0; i < 256; i++) {
- if (i%16 == 0)
- pr_debug("%04x ", i);
-
- printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i));
-
- if (i % 16 == 15)
- printk("\n");
- }
-}
-#endif
-
-static void __init sni_mem_init(void )
-{
- int i, memsize;
- struct membank {
- u32 size;
- u32 base;
- u32 size2;
- u32 pad1;
- u32 pad2;
- } memconf[8];
-
- /* MemSIZE from prom in 16MByte chunks */
- memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
-
- pr_debug("IDProm memsize: %lu MByte\n", memsize);
-
- /* get memory bank layout from prom */
- __prom_get_memconf(&memconf);
-
- pr_debug("prom_get_mem_conf memory configuration:\n");
- for (i = 0;i < 8 && memconf[i].size; i++) {
- if (sni_brd_type == SNI_BRD_PCI_TOWER ||
- sni_brd_type == SNI_BRD_PCI_TOWER_CPLUS) {
- if (memconf[i].base >= 0x20000000 &&
- memconf[i].base < 0x30000000) {
- memconf[i].base -= 0x20000000;
- }
- }
- pr_debug("Bank%d: %08x @ %08x\n", i,
- memconf[i].size, memconf[i].base);
- add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM);
- }
-}
-
-static void __init sni_console_setup(void)
-{
- char *ctype;
- char *cdev;
- char *baud;
- int port;
- static char options[8];
-
- cdev = prom_getenv("console_dev");
- if (strncmp (cdev, "tty", 3) == 0) {
- ctype = prom_getenv("console");
- switch (*ctype) {
- default:
- case 'l':
- port = 0;
- baud = prom_getenv("lbaud");
- break;
- case 'r':
- port = 1;
- baud = prom_getenv("rbaud");
- break;
- }
- if (baud)
- strcpy(options, baud);
- if (strncmp (cdev, "tty552", 6) == 0)
- add_preferred_console("ttyS", port, baud ? options : NULL);
- else
- add_preferred_console("ttySC", port, baud ? options : NULL);
- }
-}
-
-void __init prom_init(void)
-{
- int argc = fw_arg0;
- char **argv = (void *)fw_arg1;
- int i;
- int cputype;
-
- sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
- cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE;
- switch (sni_brd_type) {
- case SNI_BRD_TOWER_OASIC:
- switch (cputype) {
- case SNI_CPU_M8030:
- systype = "RM400-330";
- break;
- case SNI_CPU_M8031:
- systype = "RM400-430";
- break;
- case SNI_CPU_M8037:
- systype = "RM400-530";
- break;
- case SNI_CPU_M8034:
- systype = "RM400-730";
- break;
- default:
- systype = "RM400-xxx";
- break;
- }
- break;
- case SNI_BRD_MINITOWER:
- switch (cputype) {
- case SNI_CPU_M8021:
- case SNI_CPU_M8043:
- systype = "RM400-120";
- break;
- case SNI_CPU_M8040:
- systype = "RM400-220";
- break;
- case SNI_CPU_M8053:
- systype = "RM400-225";
- break;
- case SNI_CPU_M8050:
- systype = "RM400-420";
- break;
- default:
- systype = "RM400-xxx";
- break;
- }
- break;
- case SNI_BRD_PCI_TOWER:
- systype = "RM400-Cxx";
- break;
- case SNI_BRD_RM200:
- systype = "RM200-xxx";
- break;
- case SNI_BRD_PCI_MTOWER:
- systype = "RM300-Cxx";
- break;
- case SNI_BRD_PCI_DESKTOP:
- switch (read_c0_prid() & 0xff00) {
- case PRID_IMP_R4600:
- case PRID_IMP_R4700:
- systype = "RM200-C20";
- break;
- case PRID_IMP_R5000:
- systype = "RM200-C40";
- break;
- default:
- systype = "RM200-Cxx";
- break;
- }
- break;
- case SNI_BRD_PCI_TOWER_CPLUS:
- systype = "RM400-Exx";
- break;
- case SNI_BRD_PCI_MTOWER_CPLUS:
- systype = "RM300-Exx";
- break;
- }
- pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype);
-
-#ifdef DEBUG
- sni_idprom_dump();
-#endif
- sni_mem_init();
- sni_console_setup();
-
- /* copy prom cmdline parameters to kernel cmdline */
- for (i = 1; i < argc; i++) {
- strcat(arcs_cmdline, argv[i]);
- if (i < (argc - 1))
- strcat(arcs_cmdline, " ");
- }
-}
-
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 6f339af..796e3ce 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -178,6 +178,7 @@ void __init plat_time_init(void)
sni_a20r_timer_setup();
break;
}
+ setup_pit_timer();
}
unsigned long read_persistent_clock(void)
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b2dd9b3..c8b6625 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -200,6 +200,7 @@
#define CL_SIZE COMMAND_LINE_SIZE
+extern char *system_type;
const char *get_system_type(void);
extern unsigned long mips_machtype;
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
index ce7cff7..146d41b 100644
--- a/include/asm-mips/mipsprom.h
+++ b/include/asm-mips/mipsprom.h
@@ -71,4 +71,6 @@
#define PROM_NV_GET 53 /* XXX */
#define PROM_NV_SET 54 /* XXX */
+extern char *prom_getenv(char *);
+
#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index af08145..e716447 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -35,23 +35,23 @@ extern unsigned int sni_brd_type;
#define SNI_CPU_M8050 0x0b
#define SNI_CPU_M8053 0x0d
-#define SNI_PORT_BASE 0xb4000000
+#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
#ifndef __MIPSEL__
/*
* ASIC PCI registers for big endian configuration.
*/
-#define PCIMT_UCONF 0xbfff0004
-#define PCIMT_IOADTIMEOUT2 0xbfff000c
-#define PCIMT_IOMEMCONF 0xbfff0014
-#define PCIMT_IOMMU 0xbfff001c
-#define PCIMT_IOADTIMEOUT1 0xbfff0024
-#define PCIMT_DMAACCESS 0xbfff002c
-#define PCIMT_DMAHIT 0xbfff0034
-#define PCIMT_ERRSTATUS 0xbfff003c
-#define PCIMT_ERRADDR 0xbfff0044
-#define PCIMT_SYNDROME 0xbfff004c
-#define PCIMT_ITPEND 0xbfff0054
+#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
+#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
+#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
+#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
+#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
+#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
+#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
+#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
+#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
+#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
+#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
#define IT_INT2 0x01
#define IT_INTD 0x02
#define IT_INTC 0x04
@@ -60,32 +60,32 @@ extern unsigned int sni_brd_type;
#define IT_EISA 0x20
#define IT_SCSI 0x40
#define IT_ETH 0x80
-#define PCIMT_IRQSEL 0xbfff005c
-#define PCIMT_TESTMEM 0xbfff0064
-#define PCIMT_ECCREG 0xbfff006c
-#define PCIMT_CONFIG_ADDRESS 0xbfff0074
-#define PCIMT_ASIC_ID 0xbfff007c /* read */
-#define PCIMT_SOFT_RESET 0xbfff007c /* write */
-#define PCIMT_PIA_OE 0xbfff0084
-#define PCIMT_PIA_DATAOUT 0xbfff008c
-#define PCIMT_PIA_DATAIN 0xbfff0094
-#define PCIMT_CACHECONF 0xbfff009c
-#define PCIMT_INVSPACE 0xbfff00a4
+#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
+#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
+#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
+#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
+#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
+#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
+#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
+#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
+#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
+#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
+#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
#else
/*
* ASIC PCI registers for little endian configuration.
*/
-#define PCIMT_UCONF 0xbfff0000
-#define PCIMT_IOADTIMEOUT2 0xbfff0008
-#define PCIMT_IOMEMCONF 0xbfff0010
-#define PCIMT_IOMMU 0xbfff0018
-#define PCIMT_IOADTIMEOUT1 0xbfff0020
-#define PCIMT_DMAACCESS 0xbfff0028
-#define PCIMT_DMAHIT 0xbfff0030
-#define PCIMT_ERRSTATUS 0xbfff0038
-#define PCIMT_ERRADDR 0xbfff0040
-#define PCIMT_SYNDROME 0xbfff0048
-#define PCIMT_ITPEND 0xbfff0050
+#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
+#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
+#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
+#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
+#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
+#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
+#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
+#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
+#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
+#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
+#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
#define IT_INT2 0x01
#define IT_INTD 0x02
#define IT_INTC 0x04
@@ -94,20 +94,20 @@ extern unsigned int sni_brd_type;
#define IT_EISA 0x20
#define IT_SCSI 0x40
#define IT_ETH 0x80
-#define PCIMT_IRQSEL 0xbfff0058
-#define PCIMT_TESTMEM 0xbfff0060
-#define PCIMT_ECCREG 0xbfff0068
-#define PCIMT_CONFIG_ADDRESS 0xbfff0070
-#define PCIMT_ASIC_ID 0xbfff0078 /* read */
-#define PCIMT_SOFT_RESET 0xbfff0078 /* write */
-#define PCIMT_PIA_OE 0xbfff0080
-#define PCIMT_PIA_DATAOUT 0xbfff0088
-#define PCIMT_PIA_DATAIN 0xbfff0090
-#define PCIMT_CACHECONF 0xbfff0098
-#define PCIMT_INVSPACE 0xbfff00a0
+#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
+#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
+#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
+#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
+#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
+#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
+#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
+#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
+#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
+#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
+#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
#endif
-#define PCIMT_PCI_CONF 0xbfff0100
+#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
/*
* Data port for the PCI bus in IO space
@@ -117,34 +117,34 @@ extern unsigned int sni_brd_type;
/*
* Board specific registers
*/
-#define PCIMT_CSMSR 0xbfd00000
-#define PCIMT_CSSWITCH 0xbfd10000
-#define PCIMT_CSITPEND 0xbfd20000
-#define PCIMT_AUTO_PO_EN 0xbfd30000
-#define PCIMT_CLR_TEMP 0xbfd40000
-#define PCIMT_AUTO_PO_DIS 0xbfd50000
-#define PCIMT_EXMSR 0xbfd60000
-#define PCIMT_UNUSED1 0xbfd70000
-#define PCIMT_CSWCSM 0xbfd80000
-#define PCIMT_UNUSED2 0xbfd90000
-#define PCIMT_CSLED 0xbfda0000
-#define PCIMT_CSMAPISA 0xbfdb0000
-#define PCIMT_CSRSTBP 0xbfdc0000
-#define PCIMT_CLRPOFF 0xbfdd0000
-#define PCIMT_CSTIMER 0xbfde0000
-#define PCIMT_PWDN 0xbfdf0000
+#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
+#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
+#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
+#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
+#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
+#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
+#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
+#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
+#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
+#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
+#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
+#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
+#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
+#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
+#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
+#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
/*
* A20R based boards
*/
-#define A20R_PT_CLOCK_BASE 0xbc040000
-#define A20R_PT_TIM0_ACK 0xbc050000
-#define A20R_PT_TIM1_ACK 0xbc060000
+#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
+#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
+#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
-#define SNI_PCIT_INT_REG 0xbfff000c
+#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
#define SNI_PCIT_INT_START 24
#define SNI_PCIT_INT_END 30
@@ -186,10 +186,30 @@ extern unsigned int sni_brd_type;
/*
* Base address for the mapped 16mb EISA bus segment.
*/
-#define PCIMT_EISA_BASE 0xb0000000
+#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
/* PCI EISA Interrupt acknowledge */
-#define PCIMT_INT_ACKNOWLEDGE 0xba000000
+#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
+
+/*
+ * SNI ID PROM
+ *
+ * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities
+ * SNI_IDPROM_BRDTYPE Board Type
+ * SNI_IDPROM_CPUTYPE CPU Type on RM400
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __SNI_END 0
+#endif
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define __SNI_END 3
+#endif
+#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
+#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
+#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
+#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
+
+#define SNI_IDPROM_SIZE 0x1000
/* board specific init functions */
extern void sni_a20r_init(void);
@@ -207,6 +227,9 @@ extern void sni_pcimt_irq_init(void);
/* timer inits */
extern void sni_cpu_time_init(void);
+/* eisa init for RM200/400 */
+extern int sni_eisa_root_init(void);
+
/* common irq stuff */
extern void (*sni_hwint)(void);
extern struct irqaction sni_isa_irq;
^ permalink raw reply related
* Re: Toshiba JMR 3927 working setup?
From: Gregor Waltz @ 2008-01-04 22:27 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <20080104192310.GE22809@networkno.de>
Thiemo Seufer wrote:
> Hm, your start address is 0x80020000, but the load address of the jmr3927
> (in the www.linux-mips.org tree) is 0x80050000. So maybe the address is
> wrong, comparing with the old 2.4 kernel should tell.
>
I compared that against the working 2.4.12 kernel, which does indeed
have 80020000 in arch/mips/Makefile. I changed load-$(CONFIG...TX3927)
to use 80020000 instead of 80050000, but it still fails the same way.
There was also something that I had changed in our 2.4.12 that I had
forgotten, but my coworker reminded me that, in jmr3927.h, I changed
JMR3927_ROMCE0 from 0x1fc000000 to 0x1f000000 to have the proper
address to access some raw memory for internal purposes. I do not recall
whether that address is specific to our hardware or a typo, but I do not
think that it impacts the normal kernel anyway.
Our 2.4.12 kernel uses -mcpu=r3000 -mips1 to build the kernel. I tried
switching the arch to r3000 from r3900 in 2.6.23.9, but that did not
help. Perhaps -mips1 or an equivalent could help? I will try on Monday.
I am grasping at straws here.
Thanks to Thiemo and Florian for trying to help.
Have a good weekend.
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Gregor Waltz @ 2008-01-04 19:23 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <20080104185130.GB6532@paradigm.rfc822.org>
Florian Lohoff wrote:
> On Fri, Jan 04, 2008 at 01:40:46PM -0500, Gregor Waltz wrote:
>
>> CRC Check passed
>> Image Started At Address 0x80020000.
>> Image Length = 3424394 (0x34408a).
>> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
>> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
>>
>
> The exception comes from PMON too - Did you look up the EPC in your
> System.map file ?
>
>
>> Further, the exception gets printed immediately after "Image Length =
>> 3424394 (0x34408a)." The exception happens so soon that I doubt that the
>> kernel does very much beforehand.
>>
>
> The kernel seems to be initializing and steps upon an virtual address
> and triggers an TLB exception which as the kernel is not yet ready
> to handle it itself, thus PMONs exception handler gets triggered.
>
> My first guess is that you are catching a NULL Pointer exception
> somewhere.
>
> FLo
>
Linux 2.6.23.9:
80056eb4 T kernel_execve
My coworker built Linux 2.6.23.12 and got:
EPC=80056ee0 which does not correspond to anything in his System.map.
With a different set of tools, I also built 2.6.21.7 and got:
EPC=80056eb8 which also does not correspond to anything in the
corresponding System.map.
If this does not ring any bells, do you have any suggestions for how I
could debug this issue?
Thanks
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Thiemo Seufer @ 2008-01-04 19:23 UTC (permalink / raw)
To: Gregor Waltz; +Cc: linux-mips
In-Reply-To: <477E7DAE.2080005@raritan.com>
Gregor Waltz wrote:
> Thiemo Seufer wrote:
>> Gregor Waltz wrote:
>>
>>> I have been working on a JMR 3927 based system for a number of years. For
>>> all of that time, we have been running:
>>> binutils 2.11.90.0.1
>>> gcc 2.95.3
>>> glibc 2.2.1
>>> linux 2.4.12
>>>
>>>
>>> We want to update to a 2.6 kernel, recent build tools, and saner system
>>> libraries. Although, it seems that the JMR 3927 is still technically
>>> supported, I have not found any info on whether anybody is still running
>>> Linux on it and what combination of software they are using. Any idea?
>>> Is there a combination of software versions that are known to work on
>>> this hardware?
>>>
>>>
>>> I have used crosstool 0.43 to build:
>>> binutils 2.15
>>> gcc 3.4.5
>>> glibc 2.3.6
>>>
>>
>> http://www.linux-mips.org/wiki/Toolchains recommends binutils 2.16.1 and
>> gcc 3.4.4, but I believe your choice is also ok for 32-bit systems.
>>
>
> I will try that combination also.
>
>> Hard to tell from so little information, it would help to see the whole
>> boot log.
>>
>>
>> Thiemo
> I wish that there were more of a boot log of which to speak. The following
> is a complete boot log:
>
> Serial Number = WAC6200032
> MAC Address 1= 00:0D:5D:00:eb:6f
> Kernel Image Length = 0x695000, CRC = 0xd2ee6a23
>
> Loading Linux ......
> Downloading from ethernet, ^C to abort and restart pmonitor
> sendRRQ vmlinux.bin
> load linux length 0x34408a
> Checking CRC on downloaded RAM image
> /
> CRC Check passed
> Image Started At Address 0x80020000.
> Image Length = 3424394 (0x34408a).
> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
Hm, your start address is 0x80020000, but the load address of the jmr3927
(in the www.linux-mips.org tree) is 0x80050000. So maybe the address is
wrong, comparing with the old 2.4 kernel should tell.
> All messages before the exception are from PMON. I am booting via TFTP. I
> also tried writing the kernel to flash and booting from that, but that
> fails identically.
> I checked the other serial port on the device, but it is not showing any
> kernel messages either. The normal boot console is ttyS1. I tried setting
> the kernel parameters and the default parameters (from the kernel build
> config) to "console=ttyS1", but that made no difference. Regardless, I
> would think that the kernel knows where to send messages because I am
> seeing the exception dump on ttyS1.
> Further, the exception gets printed immediately after "Image Length =
> 3424394 (0x34408a)." The exception happens so soon that I doubt that the
> kernel does very much beforehand.
True, it fails early, before it can take over the exception handlers.
Thiemo
^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Florian Lohoff @ 2008-01-04 18:51 UTC (permalink / raw)
To: Gregor Waltz; +Cc: linux-mips
In-Reply-To: <477E7DAE.2080005@raritan.com>
[-- Attachment #1: Type: text/plain, Size: 1058 bytes --]
On Fri, Jan 04, 2008 at 01:40:46PM -0500, Gregor Waltz wrote:
> CRC Check passed
> Image Started At Address 0x80020000.
> Image Length = 3424394 (0x34408a).
> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
The exception comes from PMON too - Did you look up the EPC in your
System.map file ?
> Further, the exception gets printed immediately after "Image Length =
> 3424394 (0x34408a)." The exception happens so soon that I doubt that the
> kernel does very much beforehand.
The kernel seems to be initializing and steps upon an virtual address
and triggers an TLB exception which as the kernel is not yet ready
to handle it itself, thus PMONs exception handler gets triggered.
My first guess is that you are catching a NULL Pointer exception
somewhere.
FLo
--
Florian Lohoff flo@rfc822.org +49-171-2280134
Those who would give up a little freedom to get a little
security shall soon have neither - Benjamin Franklin
[-- Attachment #2: Digital signature --]
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^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Gregor Waltz @ 2008-01-04 18:40 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <20080104172136.GD22809@networkno.de>
Thiemo Seufer wrote:
> Gregor Waltz wrote:
>
>> I have been working on a JMR 3927 based system for a number of years. For
>> all of that time, we have been running:
>> binutils 2.11.90.0.1
>> gcc 2.95.3
>> glibc 2.2.1
>> linux 2.4.12
>>
>>
>> We want to update to a 2.6 kernel, recent build tools, and saner system
>> libraries. Although, it seems that the JMR 3927 is still technically
>> supported, I have not found any info on whether anybody is still running
>> Linux on it and what combination of software they are using. Any idea?
>> Is there a combination of software versions that are known to work on this
>> hardware?
>>
>>
>> I have used crosstool 0.43 to build:
>> binutils 2.15
>> gcc 3.4.5
>> glibc 2.3.6
>>
>
> http://www.linux-mips.org/wiki/Toolchains recommends binutils 2.16.1 and
> gcc 3.4.4, but I believe your choice is also ok for 32-bit systems.
>
I will try that combination also.
> Hard to tell from so little information, it would help to see the whole
> boot log.
>
>
> Thiemo
I wish that there were more of a boot log of which to speak. The
following is a complete boot log:
Serial Number = WAC6200032
MAC Address 1= 00:0D:5D:00:eb:6f
Kernel Image Length = 0x695000, CRC = 0xd2ee6a23
Loading Linux ......
Downloading from ethernet, ^C to abort and restart pmonitor
sendRRQ vmlinux.bin
load linux length 0x34408a
Checking CRC on downloaded RAM image
/
CRC Check passed
Image Started At Address 0x80020000.
Image Length = 3424394 (0x34408a).
Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
80056eb4 8ce4000c lw a0,12(a3) # 0xc
All messages before the exception are from PMON. I am booting via TFTP.
I also tried writing the kernel to flash and booting from that, but that
fails identically.
I checked the other serial port on the device, but it is not showing any
kernel messages either. The normal boot console is ttyS1. I tried
setting the kernel parameters and the default parameters (from the
kernel build config) to "console=ttyS1", but that made no difference.
Regardless, I would think that the kernel knows where to send messages
because I am seeing the exception dump on ttyS1.
Further, the exception gets printed immediately after "Image Length =
3424394 (0x34408a)." The exception happens so soon that I doubt that the
kernel does very much beforehand.
Thanks
^ permalink raw reply
* RE: BUS error while returning from read() in /dev/oprofile/buffer
From: Anirban Sinha @ 2008-01-04 17:56 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <DDFD17CC94A9BD49A82147DDF7D545C56440FC@exchange.ZeugmaSystems.local>
[-- Attachment #1: Type: text/plain, Size: 1554 bytes --]
First a correction. My test program does terminate with a bus error on
receiving signal USR1. Just in case anyone is interested - It turned out
that the BUS error results from the fact that when coreutils was built,
it used the signal numbers from the devel machine (x86). These numbers
are different from our mips kernel on which we want to use oprofile
(mips has slightly different signal numbers from x86). Many thanks to
David Daney for drawing my attention to this.
Cheers,
Ani
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Anirban Sinha
Sent: Thursday, January 03, 2008 5:18 PM
To: linux-mips@linux-mips.org; Ralf Baechle
Subject: BUG: BUS error while returning from read() in
/dev/oprofile/buffer
Hi:
I have been trying to hunt down this bug for several days now. What
mainly happens is that when oprofiled wakes up from read() in
/dev/oprofile/buffer on receiving a signal USR1 (i.e, when someone does
opcontrol -start after doing opcontrol-start-daemon), it somehow gets
SIGBUS within glibc read(). We are using a mips machine with Sybyte SB1
processor. On intel, this error does not show up. Interestingly, when I
tried running a small test program that simply reads
/dev/oprofile/buffer, the error can't be reproduced!
Ralf and others, any insights, suggestions or useful comments from
experience will be really really appreciated. I am spending a lot of
time trying to fix this bug.
Cheers,
Ani
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^ permalink raw reply
* RE: BUS error while returning from read() in /dev/oprofile/buffer
From: Anirban Sinha @ 2008-01-04 17:56 UTC (permalink / raw)
To: linux-mips
In-Reply-To: <DDFD17CC94A9BD49A82147DDF7D545C56440FC@exchange.ZeugmaSystems.local>
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First a correction. My test program does terminate with a bus error on
receiving signal USR1. Just in case anyone is interested - It turned out
that the BUS error results from the fact that when coreutils was built,
it used the signal numbers from the devel machine (x86). These numbers
are different from our mips kernel on which we want to use oprofile
(mips has slightly different signal numbers from x86). Many thanks to
David Daney for drawing my attention to this.
Cheers,
Ani
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Anirban Sinha
Sent: Thursday, January 03, 2008 5:18 PM
To: linux-mips@linux-mips.org; Ralf Baechle
Subject: BUG: BUS error while returning from read() in
/dev/oprofile/buffer
Hi:
I have been trying to hunt down this bug for several days now. What
mainly happens is that when oprofiled wakes up from read() in
/dev/oprofile/buffer on receiving a signal USR1 (i.e, when someone does
opcontrol -start after doing opcontrol-start-daemon), it somehow gets
SIGBUS within glibc read(). We are using a mips machine with Sybyte SB1
processor. On intel, this error does not show up. Interestingly, when I
tried running a small test program that simply reads
/dev/oprofile/buffer, the error can't be reproduced!
Ralf and others, any insights, suggestions or useful comments from
experience will be really really appreciated. I am spending a lot of
time trying to fix this bug.
Cheers,
Ani
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^ permalink raw reply
* Re: Toshiba JMR 3927 working setup?
From: Thiemo Seufer @ 2008-01-04 17:21 UTC (permalink / raw)
To: Gregor Waltz; +Cc: linux-mips
In-Reply-To: <477E6296.7090605@raritan.com>
Gregor Waltz wrote:
> I have been working on a JMR 3927 based system for a number of years. For
> all of that time, we have been running:
> binutils 2.11.90.0.1
> gcc 2.95.3
> glibc 2.2.1
> linux 2.4.12
>
>
> We want to update to a 2.6 kernel, recent build tools, and saner system
> libraries. Although, it seems that the JMR 3927 is still technically
> supported, I have not found any info on whether anybody is still running
> Linux on it and what combination of software they are using. Any idea?
> Is there a combination of software versions that are known to work on this
> hardware?
>
>
> I have used crosstool 0.43 to build:
> binutils 2.15
> gcc 3.4.5
> glibc 2.3.6
http://www.linux-mips.org/wiki/Toolchains recommends binutils 2.16.1 and
gcc 3.4.4, but I believe your choice is also ok for 32-bit systems.
> I cannot get these kernels to build:
> linux-2.6.13
> linux-2.6.15
> linux-2.6.16.57
> linux-2.6.17.14
> linux-2.6.9
>
> My colleague and I have built these:
> linux-2.6.21.7
> linux-2.6.23.9
> linux-2.6.23.12
>
> However, they all yield a TLBL exception similar to the following:
>
> Exception! EPC=80056eb4 CAUSE=30000008(TLBL)
> 80056eb4 8ce4000c lw a0,12(a3) # 0xc
>
> Each build has different exception values. The values are the same each
> attempt with the same build.
>
> Is this a problem in the kernel code or the build tools?
> Any ideas on how to make it run?
Hard to tell from so little information, it would help to see the whole
boot log.
Thiemo
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