* Re: [PATCH] riscv: Add native this_cpu_cmpxchg() support
[not found] <20260730094407.16588-1-xb@ultrarisc.com>
@ 2026-08-21 1:27 ` Paul Walmsley
0 siblings, 0 replies; only message in thread
From: Paul Walmsley @ 2026-08-21 1:27 UTC (permalink / raw)
To: Xie Bo
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-riscv, Dennis Zhou, Tejun Heo, Christoph Lameter,
Jonathan Corbet, Shuah Khan, linux-mm, linux-doc, linux-kernel
Hi,
On Thu, 30 Jul 2026, Xie Bo wrote:
> RISC-V falls back to the generic this_cpu_cmpxchg() implementation,
> which serializes the operation by disabling local interrupts.
> Consequently, HAVE_CMPXCHG_LOCAL is unset and users such as
> percpu_counter cannot use their cmpxchg-based fast paths.
>
> Implement the 4-byte this_cpu_cmpxchg() operation with cmpxchg_local(),
> and provide the 8-byte operation on RV64. Pin execution while resolving
> the current CPU pointer so the LR/SC loop operates on one per-CPU
> instance, while allowing interrupt-context updates to race through the
> atomic operation.
>
> Copy the old and new values to private temporaries before invoking
> cmpxchg_local(). This avoids collisions between local variable names in
> nested statement-expression macros.
>
> The 1- and 2-byte operations continue to use the generic fallback.
>
> Select HAVE_CMPXCHG_LOCAL and update the architecture feature matrix.
>
> A percpu_counter_add() benchmark using the default batch value reduced
> the median time per operation by 77.3% (10 runs of 5,000,000
> operations).
>
> In three 60-second stress-ng fork runs, median throughput increased by
> 4.6%. A 120-second combined fork and VM stress test completed without
> rss-counter errors or validation failures.
>
> Signed-off-by: Xie Bo <xb@ultrarisc.com>
This patch seems to be missing 128-bit cmpxchg support. Care to add it?
thanks,
- Paul
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