[PATCH 1/2] mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for Rockchip SOCs

[PATCH 1/2] mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for Rockchip SOCs

[Shawn Lin]

Enabling CMDQ support can lead to random occurrences of the error log when
there are RPMB access and data flush executed:

"mmc2: Timeout waiting for hardware interrupt."

Enabling CMDQ and then issuing a DCMD as the final command before disabling
it causes the eMMC controller to auto-gate its internal clock. Chip simulation
shows this results in a state machine mismatch after CMDQ mode exit, triggering
data-timeout errors for all subsequent read and write operations.

Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
enabled.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

 drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index c66a8df..e276a4e 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -713,10 +713,11 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
 
 	sdhci_set_clock(host, clock);
 
-	/* Disable cmd conflict check */
+	/* Disable cmd conflict check and internal clock gate */
 	reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
 	extra = sdhci_readl(host, reg);
 	extra &= ~BIT(0);
+	extra |= BIT(4);
 	sdhci_writel(host, extra, reg);
 
 	if (clock <= 52000000) {
-- 
2.7.4

[PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Shawn Lin]

CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
hardware queue, and CMD13 can only query one slot at a time for data
transmission, which cannot be processed in parallel. Modifying the
CMD13 query interval can increase the query frequency and improve
random write performance.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

 drivers/mmc/host/cqhci.h            | 1 +
 drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index ce189a1..3668856 100644
--- a/drivers/mmc/host/cqhci.h
+++ b/drivers/mmc/host/cqhci.h
@@ -93,6 +93,7 @@
 /* send status config 1 */
 #define CQHCI_SSC1			0x40
 #define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
+#define CQHCI_SSC1_CIT_MASK		GENMASK(15, 0)
 
 /* send status config 2 */
 #define CQHCI_SSC2			0x44
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index e276a4e..cad5165 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
 	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 	u32 reg;
 
+	/* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
+	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
+	reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
+	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
+
 	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
 	reg |= CQHCI_ENABLE;
 	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
-- 
2.7.4

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Ulf Hansson]

+ cqhci maintainers (Adrian, Asutosh, Ritesh)

On Wed, 12 Nov 2025 at 08:44, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
> periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
> hardware queue, and CMD13 can only query one slot at a time for data
> transmission, which cannot be processed in parallel. Modifying the
> CMD13 query interval can increase the query frequency and improve
> random write performance.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

No strong opinion on this, but I looped in the cqhci maintainers to
allow them to chime in.

Kind regards
Uffe

> ---
>
>  drivers/mmc/host/cqhci.h            | 1 +
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index ce189a1..3668856 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -93,6 +93,7 @@
>  /* send status config 1 */
>  #define CQHCI_SSC1                     0x40
>  #define CQHCI_SSC1_CBC_MASK            GENMASK(19, 16)
> +#define CQHCI_SSC1_CIT_MASK            GENMASK(15, 0)
>
>  /* send status config 2 */
>  #define CQHCI_SSC2                     0x44
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index e276a4e..cad5165 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
>         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
>         u32 reg;
>
> +       /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
> +       reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> +       reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
> +       sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> +
>         reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>         reg |= CQHCI_ENABLE;
>         sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
> --
> 2.7.4
>

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Adrian Hunter]

On 12/11/2025 14:03, Ulf Hansson wrote:
> + cqhci maintainers (Adrian, Asutosh, Ritesh)
> 
> On Wed, 12 Nov 2025 at 08:44, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>>
>> CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
>> periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
>> hardware queue, and CMD13 can only query one slot at a time for data
>> transmission, which cannot be processed in parallel. Modifying the
>> CMD13 query interval can increase the query frequency and improve
>> random write performance.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> No strong opinion on this, but I looped in the cqhci maintainers to
> allow them to chime in.

cqhci-core leaves CQHCI_SSC1 configuration to the default values
or for drivers to set for themselves.  When it comes to timing
values, eMMC has not really been one-size-fits-all, so that seems
appropriate.

So for both patches:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> 
> Kind regards
> Uffe
> 
>> ---
>>
>>  drivers/mmc/host/cqhci.h            | 1 +
>>  drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
>>  2 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
>> index ce189a1..3668856 100644
>> --- a/drivers/mmc/host/cqhci.h
>> +++ b/drivers/mmc/host/cqhci.h
>> @@ -93,6 +93,7 @@
>>  /* send status config 1 */
>>  #define CQHCI_SSC1                     0x40
>>  #define CQHCI_SSC1_CBC_MASK            GENMASK(19, 16)
>> +#define CQHCI_SSC1_CIT_MASK            GENMASK(15, 0)
>>
>>  /* send status config 2 */
>>  #define CQHCI_SSC2                     0x44
>> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
>> index e276a4e..cad5165 100644
>> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
>> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
>> @@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
>>         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
>>         u32 reg;
>>
>> +       /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
>> +       reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
>> +       reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
>> +       sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
>> +
>>         reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>>         reg |= CQHCI_ENABLE;
>>         sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>> --
>> 2.7.4
>>

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Shawn Lin]

在 2025/11/12 星期三 15:44, Shawn Lin 写道:
> CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
> periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
> hardware queue, and CMD13 can only query one slot at a time for data
> transmission, which cannot be processed in parallel. Modifying the
> CMD13 query interval can increase the query frequency and improve
> random write performance.
> 

Ping...

Adrain acked these two patches, so will them be candidates for 6.19
given the merge windows is coming soon?

> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> 
>   drivers/mmc/host/cqhci.h            | 1 +
>   drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index ce189a1..3668856 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -93,6 +93,7 @@
>   /* send status config 1 */
>   #define CQHCI_SSC1			0x40
>   #define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
> +#define CQHCI_SSC1_CIT_MASK		GENMASK(15, 0)
>   
>   /* send status config 2 */
>   #define CQHCI_SSC2			0x44
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index e276a4e..cad5165 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
>   	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
>   	u32 reg;
>   
> +	/* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
> +	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> +	reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
> +	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> +
>   	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>   	reg |= CQHCI_ENABLE;
>   	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Ulf Hansson]

On Tue, 25 Nov 2025 at 14:58, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> 在 2025/11/12 星期三 15:44, Shawn Lin 写道:
> > CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
> > periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
> > hardware queue, and CMD13 can only query one slot at a time for data
> > transmission, which cannot be processed in parallel. Modifying the
> > CMD13 query interval can increase the query frequency and improve
> > random write performance.
> >
>
> Ping...
>
> Adrain acked these two patches, so will them be candidates for 6.19
> given the merge windows is coming soon?

Looks like I simply failed to see them. Possibly because there was
cover-letter, which makes it harder for me to follow all the different
series.

Anyway, I tried to apply them, but there are conflicts that I am not
sure I can resolve easily by myself. Would you mind doing a re-base
and post a new version, then I can apply them asap.

Kind regards
Uffe

>
> > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> > ---
> >
> >   drivers/mmc/host/cqhci.h            | 1 +
> >   drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
> >   2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> > index ce189a1..3668856 100644
> > --- a/drivers/mmc/host/cqhci.h
> > +++ b/drivers/mmc/host/cqhci.h
> > @@ -93,6 +93,7 @@
> >   /* send status config 1 */
> >   #define CQHCI_SSC1                  0x40
> >   #define CQHCI_SSC1_CBC_MASK         GENMASK(19, 16)
> > +#define CQHCI_SSC1_CIT_MASK          GENMASK(15, 0)
> >
> >   /* send status config 2 */
> >   #define CQHCI_SSC2                  0x44
> > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > index e276a4e..cad5165 100644
> > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > @@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
> >       struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
> >       u32 reg;
> >
> > +     /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
> > +     reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> > +     reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
> > +     sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
> > +
> >       reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
> >       reg |= CQHCI_ENABLE;
> >       sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Ulf Hansson]

On Tue, 25 Nov 2025 at 17:02, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>
> On Tue, 25 Nov 2025 at 14:58, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> >
> > 在 2025/11/12 星期三 15:44, Shawn Lin 写道:
> > > CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
> > > periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
> > > hardware queue, and CMD13 can only query one slot at a time for data
> > > transmission, which cannot be processed in parallel. Modifying the
> > > CMD13 query interval can increase the query frequency and improve
> > > random write performance.
> > >
> >
> > Ping...
> >
> > Adrain acked these two patches, so will them be candidates for 6.19
> > given the merge windows is coming soon?
>
> Looks like I simply failed to see them. Possibly because there was
> cover-letter, which makes it harder for me to follow all the different

/s/cover-letter/no cover-letter

[...]

Kind regards
Uffe

Re: [PATCH 2/2] mmc: sdhci-of-dwcmshc: reduce CIT for better performance

[Shawn Lin]

在 2025/11/26 星期三 0:02, Ulf Hansson 写道:
> On Tue, 25 Nov 2025 at 14:58, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>>
>> 在 2025/11/12 星期三 15:44, Shawn Lin 写道:
>>> CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
>>> periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
>>> hardware queue, and CMD13 can only query one slot at a time for data
>>> transmission, which cannot be processed in parallel. Modifying the
>>> CMD13 query interval can increase the query frequency and improve
>>> random write performance.
>>>
>>
>> Ping...
>>
>> Adrain acked these two patches, so will them be candidates for 6.19
>> given the merge windows is coming soon?
> 
> Looks like I simply failed to see them. Possibly because there was
> cover-letter, which makes it harder for me to follow all the different
> series.
> 
> Anyway, I tried to apply them, but there are conflicts that I am not
> sure I can resolve easily by myself. Would you mind doing a re-base
> and post a new version, then I can apply them asap.
> 

Thanks Ulf. I just did a rebase on top of linux-next and posted a new
version[1].

[1] 
https://lore.kernel.org/all/1764113200-237279-1-git-send-email-shawn.lin@rock-chips.com/


> Kind regards
> Uffe
> 
>>
>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>> ---
>>>
>>>    drivers/mmc/host/cqhci.h            | 1 +
>>>    drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
>>>    2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
>>> index ce189a1..3668856 100644
>>> --- a/drivers/mmc/host/cqhci.h
>>> +++ b/drivers/mmc/host/cqhci.h
>>> @@ -93,6 +93,7 @@
>>>    /* send status config 1 */
>>>    #define CQHCI_SSC1                  0x40
>>>    #define CQHCI_SSC1_CBC_MASK         GENMASK(19, 16)
>>> +#define CQHCI_SSC1_CIT_MASK          GENMASK(15, 0)
>>>
>>>    /* send status config 2 */
>>>    #define CQHCI_SSC2                  0x44
>>> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
>>> index e276a4e..cad5165 100644
>>> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
>>> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
>>> @@ -631,6 +631,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
>>>        struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
>>>        u32 reg;
>>>
>>> +     /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
>>> +     reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
>>> +     reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
>>> +     sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
>>> +
>>>        reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>>>        reg |= CQHCI_ENABLE;
>>>        sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
>>
>