[PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check

[PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check

[Shawn Guo]

From: Shawn Guo <shawn.guo@linaro.org>

As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz.  Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one).  Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50.  Separate the
check to support such system design.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a20459744d21..aa45901325b9 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 			 * Do not advertise faster UHS modes if there are no
 			 * pinctrl states for 100MHz/200MHz.
 			 */
-			if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
-			    IS_ERR_OR_NULL(imx_data->pins_200mhz))
-				val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
-					 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
+			if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
+				val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+			if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
+				val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 		}
 	}
 
-- 
2.17.1

RE: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check

[Bough Chen]

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> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2021年3月26日 19:02
> To: Adrian Hunter <adrian.hunter@intel.com>; Ulf Hansson
> <ulf.hansson@linaro.org>
> Cc: Bough Chen <haibo.chen@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>;
> linux-mmc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Shawn Guo
> <shawn.guo@linaro.org>
> Subject: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states
> check
> 
> From: Shawn Guo <shawn.guo@linaro.org>
> 
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50 require
> pins_100mhz, while SDR104 and HS400 require pins_200mhz.  Some system
> design may support SDR50 and DDR50 with 100mhz pin state only (without
> 200mhz one).  Currently the combined 100/200 MHz pinctrl state check
> prevents such system from running SDR50 and DDR50.  Separate the check to
> support such system design.
> 
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host,
> int reg)
>  			 * Do not advertise faster UHS modes if there are no
>  			 * pinctrl states for 100MHz/200MHz.
>  			 */
> -			if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> -			    IS_ERR_OR_NULL(imx_data->pins_200mhz))
> -				val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50
> -					 | SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> +			if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> +				val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50);
> +			if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> +				val &= ~(SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
>  		}
>  	}
> 
> --
> 2.17.1


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Re: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check

[Ulf Hansson]

On Fri, 26 Mar 2021 at 12:02, Shawn Guo <shawnguo@kernel.org> wrote:
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
> require pins_100mhz, while SDR104 and HS400 require pins_200mhz.  Some
> system design may support SDR50 and DDR50 with 100mhz pin state only
> (without 200mhz one).  Currently the combined 100/200 MHz pinctrl state
> check prevents such system from running SDR50 and DDR50.  Separate the
> check to support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
>                          * Do not advertise faster UHS modes if there are no
>                          * pinctrl states for 100MHz/200MHz.
>                          */
> -                       if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> -                           IS_ERR_OR_NULL(imx_data->pins_200mhz))
> -                               val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
> -                                        | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> +                       if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> +                               val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> +                       if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> +                               val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
>                 }
>         }
>
> --
> 2.17.1
>