[PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[Anand Moon]

As per RK3588 TRM Part 2 section EMMC_EMMC_CTRL, Add code to enable
enhanced strobe mode, set the card type to eMMC in HS400 during clock
configuration. This bit instructs Host to sample the CMD line using data
strobe for HS400 mode.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index eebd453899566..3edde4532b13c 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -77,6 +77,10 @@
 #define CV18XX_RETRY_TUNING_MAX			50
 
 /* Rockchip specific Registers */
+#define DWCMSHC_EMMC_CTRL		0x52c
+#define  EMMC_CTRL_CARD_IS_EMMC		BIT(0)
+#define  EMMC_CTRL_ENH_STROBE_ENABLE	BIT(8)
+
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
 #define DWCMSHC_EMMC_DLL_RXCLK		0x804
 #define DWCMSHC_EMMC_DLL_TXCLK		0x808
@@ -660,6 +664,14 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
 			DLL_CMDOUT_TAPNUM_90_DEGREES |
 			DLL_CMDOUT_TAPNUM_FROM_SW;
 		sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+
+		extra = sdhci_readl(host, DWCMSHC_EMMC_CTRL);
+		if (extra & EMMC_CTRL_CARD_IS_EMMC) {
+			extra |= EMMC_CTRL_ENH_STROBE_ENABLE;
+			sdhci_writel(host, extra, DWCMSHC_EMMC_CTRL);
+		} else {
+			dev_info(mmc_dev(host->mmc), "strobe mode not enabled!\n");
+		}
 	}
 
 	extra = DWCMSHC_EMMC_DLL_DLYENA |

base-commit: 4427259cc7f7571a157fbc9b5011e1ef6fe0a4a8
-- 
2.50.1

Re: [PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[Shawn Lin]

在 2025/11/11 星期二 15:21, Anand Moon 写道:
> As per RK3588 TRM Part 2 section EMMC_EMMC_CTRL, Add code to enable
> enhanced strobe mode, set the card type to eMMC in HS400 during clock
> configuration. This bit instructs Host to sample the CMD line using data
> strobe for HS400 mode.
> 

Did you really test the latest kernel?
HS400ES for Rockchip platform has been supported for 3 years..

please see commit c6f361cba51c536e7a6af31973c6a4e5d7e4e2e4

> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>   drivers/mmc/host/sdhci-of-dwcmshc.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index eebd453899566..3edde4532b13c 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -77,6 +77,10 @@
>   #define CV18XX_RETRY_TUNING_MAX			50
>   
>   /* Rockchip specific Registers */
> +#define DWCMSHC_EMMC_CTRL		0x52c
> +#define  EMMC_CTRL_CARD_IS_EMMC		BIT(0)
> +#define  EMMC_CTRL_ENH_STROBE_ENABLE	BIT(8)
> +
>   #define DWCMSHC_EMMC_DLL_CTRL		0x800
>   #define DWCMSHC_EMMC_DLL_RXCLK		0x804
>   #define DWCMSHC_EMMC_DLL_TXCLK		0x808
> @@ -660,6 +664,14 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
>   			DLL_CMDOUT_TAPNUM_90_DEGREES |
>   			DLL_CMDOUT_TAPNUM_FROM_SW;
>   		sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
> +
> +		extra = sdhci_readl(host, DWCMSHC_EMMC_CTRL);
> +		if (extra & EMMC_CTRL_CARD_IS_EMMC) {
> +			extra |= EMMC_CTRL_ENH_STROBE_ENABLE;
> +			sdhci_writel(host, extra, DWCMSHC_EMMC_CTRL);
> +		} else {
> +			dev_info(mmc_dev(host->mmc), "strobe mode not enabled!\n");
> +		}
>   	}
>   
>   	extra = DWCMSHC_EMMC_DLL_DLYENA |
> 
> base-commit: 4427259cc7f7571a157fbc9b5011e1ef6fe0a4a8

Re: [PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[Anand Moon]

Hi Shawn,

Thanks for your review comments.
On Tue, 11 Nov 2025 at 13:09, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> 在 2025/11/11 星期二 15:21, Anand Moon 写道:
> > As per RK3588 TRM Part 2 section EMMC_EMMC_CTRL, Add code to enable
> > enhanced strobe mode, set the card type to eMMC in HS400 during clock
> > configuration. This bit instructs Host to sample the CMD line using data
> > strobe for HS400 mode.
> >
>
> Did you really test the latest kernel?
Yes, with the fio command, testing before and after this patch on a
Radxa Rock 5b eMMC.

$ dmesg | grep mmc
[   16.321495] [     T60] mmc0: SDHCI controller on fe2e0000.mmc
[fe2e0000.mmc] using ADMA
[   16.425317] [     T72] mmc0: new HS400 Enhanced strobe MMC card at
address 0001
[   16.449670] [     T72] mmcblk0: mmc0:0001 SLD64G 57.6 GiB
[   16.550133] [     T72]  mmcblk0: p1 p2
[   16.577289] [     T72] mmcblk0boot0: mmc0:0001 SLD64G 4.00 MiB
[   16.641182] [     T72] mmcblk0boot1: mmc0:0001 SLD64G 4.00 MiB
[   16.699865] [     T72] mmcblk0rpmb: mmc0:0001 SLD64G 4.00 MiB,
chardev (234:0)

> HS400ES for Rockchip platform has been supported for 3 years..
>
The only modification made was to enable the strobe bit in the eMMC control.
> please see commit c6f361cba51c536e7a6af31973c6a4e5d7e4e2e4
>
Based on my analysis and the RK3568 TRM, neither the RK3566 nor the
RK2568 supports
HS200 or HS400 modes.

Thanks
-Anand

Re: [PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[Shawn Lin]

+ Fukaumi-sang

在 2025/11/11 星期二 17:11, Anand Moon 写道:
> Hi Shawn,
> 
> Thanks for your review comments.
> On Tue, 11 Nov 2025 at 13:09, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>>
>> 在 2025/11/11 星期二 15:21, Anand Moon 写道:
>>> As per RK3588 TRM Part 2 section EMMC_EMMC_CTRL, Add code to enable
>>> enhanced strobe mode, set the card type to eMMC in HS400 during clock
>>> configuration. This bit instructs Host to sample the CMD line using data
>>> strobe for HS400 mode.
>>>
>>
>> Did you really test the latest kernel?
> Yes, with the fio command, testing before and after this patch on a
> Radxa Rock 5b eMMC.


The commit msg says RK3588, but it already supported enhanced strobe...

Quote a boot log from V6.18-rc5 of a RK3588 board without any patch:

[    0.544447] mmc0: new HS400 Enhanced strobe MMC card at address 0001
[    0.545540] mmcblk0: mmc0:0001 BJTD4R 29.1 GiB
[    0.548983]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8
[    0.550874] mmcblk0boot0: mmc0:0001 BJTD4R 4.00 MiB
[    0.552682] mmcblk0boot1: mmc0:0001 BJTD4R 4.00 MiB
[    0.554334] mmcblk0rpmb: mmc0:0001 BJTD4R 4.00 MiB, chardev (509:0)

So the whole patch makes no sense.

> 
> $ dmesg | grep mmc
> [   16.321495] [     T60] mmc0: SDHCI controller on fe2e0000.mmc
> [fe2e0000.mmc] using ADMA
> [   16.425317] [     T72] mmc0: new HS400 Enhanced strobe MMC card at
> address 0001
> [   16.449670] [     T72] mmcblk0: mmc0:0001 SLD64G 57.6 GiB
> [   16.550133] [     T72]  mmcblk0: p1 p2
> [   16.577289] [     T72] mmcblk0boot0: mmc0:0001 SLD64G 4.00 MiB
> [   16.641182] [     T72] mmcblk0boot1: mmc0:0001 SLD64G 4.00 MiB
> [   16.699865] [     T72] mmcblk0rpmb: mmc0:0001 SLD64G 4.00 MiB,
> chardev (234:0)
> 
>> HS400ES for Rockchip platform has been supported for 3 years..
>>
> The only modification made was to enable the strobe bit in the eMMC control.

sdhci_dwcmshc_rk35xx_ops->dwcmshc_set_uhs_signaling（） set it... please
check the code.

>> please see commit c6f361cba51c536e7a6af31973c6a4e5d7e4e2e4
>>
> Based on my analysis and the RK3568 TRM, neither the RK3566 nor the
> RK2568 supports
> HS200 or HS400 modes.

There is no a chip called RK2568, so I assume you meant RK3568?
RK3566/RK3568 support HS200, but not HS400（HS400ES also）, so we didn't
add properties in the DT. This is not because of the code, but the
chip design reason.


> 
> Thanks
> -Anand
> 

Re: [PATCH v1] mmc: sdhci-of-dwcmshc: Enable enhanced strobe for eMMC in HS400 for Rockchip

[Anand Moon]

Hi Shawn

On Tue, 11 Nov 2025 at 15:04, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> + Fukaumi-sang
>
> 在 2025/11/11 星期二 17:11, Anand Moon 写道:
> > Hi Shawn,
> >
> > Thanks for your review comments.
> > On Tue, 11 Nov 2025 at 13:09, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> >>
> >> 在 2025/11/11 星期二 15:21, Anand Moon 写道:
> >>> As per RK3588 TRM Part 2 section EMMC_EMMC_CTRL, Add code to enable
> >>> enhanced strobe mode, set the card type to eMMC in HS400 during clock
> >>> configuration. This bit instructs Host to sample the CMD line using data
> >>> strobe for HS400 mode.
> >>>
> >>
> >> Did you really test the latest kernel?
> > Yes, with the fio command, testing before and after this patch on a
> > Radxa Rock 5b eMMC.
>
>
> The commit msg says RK3588, but it already supported enhanced strobe...
>
> Quote a boot log from V6.18-rc5 of a RK3588 board without any patch:
>
> [    0.544447] mmc0: new HS400 Enhanced strobe MMC card at address 0001
> [    0.545540] mmcblk0: mmc0:0001 BJTD4R 29.1 GiB
> [    0.548983]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8
> [    0.550874] mmcblk0boot0: mmc0:0001 BJTD4R 4.00 MiB
> [    0.552682] mmcblk0boot1: mmc0:0001 BJTD4R 4.00 MiB
> [    0.554334] mmcblk0rpmb: mmc0:0001 BJTD4R 4.00 MiB, chardev (509:0)
>
I was checking if the else part was true.
> So the whole patch makes no sense.
>
I've attempted configuration based on the TRM specification.
If it causes issues, feel free to disregard this patch.
Sorry for the noise.

$ sudo mmc extcsd read /dev/mmcblk0
[sudo] password for alarm:
=============================================
  Extended CSD rev 1.8 (MMC 5.1)
=============================================

Card Supported Command sets [S_CMD_SET: 0x01]
HPI Features [HPI_FEATURE: 0x01]: implementation based on CMD13
Background operations support [BKOPS_SUPPORT: 0x01]
Max Packet Read Cmd [MAX_PACKED_READS: 0x3f]
Max Packet Write Cmd [MAX_PACKED_WRITES: 0x3f]
Data TAG support [DATA_TAG_SUPPORT: 0x01]
Data TAG Unit Size [TAG_UNIT_SIZE: 0x03]
Tag Resources Size [TAG_RES_SIZE: 0x00]
Context Management Capabilities [CONTEXT_CAPABILITIES: 0x05]
Large Unit Size [LARGE_UNIT_SIZE_M1: 0x07]
Extended partition attribute support [EXT_SUPPORT: 0x03]
Generic CMD6 Timer [GENERIC_CMD6_TIME: 0x0a]
Power off notification [POWER_OFF_LONG_TIME: 0x3c]
Cache Size [CACHE_SIZE] is 8192 KiB
Background operations status [BKOPS_STATUS: 0x00]
1st Initialisation Time after programmed sector [INI_TIMEOUT_AP: 0x1e]
Power class for 52MHz, DDR at 3.6V [PWR_CL_DDR_52_360: 0x00]
Power class for 52MHz, DDR at 1.95V [PWR_CL_DDR_52_195: 0x00]
Power class for 200MHz at 3.6V [PWR_CL_200_360: 0x00]
Power class for 200MHz, at 1.95V [PWR_CL_200_195: 0x00]
Minimum Performance for 8bit at 52MHz in DDR mode:
 [MIN_PERF_DDR_W_8_52: 0x00]
 [MIN_PERF_DDR_R_8_52: 0x00]
TRIM Multiplier [TRIM_MULT: 0x05]
Secure Feature support [SEC_FEATURE_SUPPORT: 0x55]
Boot Information [BOOT_INFO: 0x07]
 Device supports alternative boot method
 Device supports dual data rate during boot
 Device supports high speed timing during boot
Boot partition size [BOOT_SIZE_MULTI: 0x20]
Access size [ACC_SIZE: 0x06]
High-capacity erase unit size [HC_ERASE_GRP_SIZE: 0x01]
 i.e. 512 KiB
High-capacity erase timeout [ERASE_TIMEOUT_MULT: 0x05]
Reliable write sector count [REL_WR_SEC_C: 0x01]
High-capacity W protect group size [HC_WP_GRP_SIZE: 0x10]
 i.e. 8192 KiB
Sleep current (VCC) [S_C_VCC: 0x07]
Sleep current (VCCQ) [S_C_VCCQ: 0x07]
Sleep/awake timeout [S_A_TIMEOUT: 0x16]
Sector Count [SEC_COUNT: 0x0733c000]
 Device is block-addressed
Minimum Write Performance for 8bit:
 [MIN_PERF_W_8_52: 0x00]
 [MIN_PERF_R_8_52: 0x00]
 [MIN_PERF_W_8_26_4_52: 0x00]
 [MIN_PERF_R_8_26_4_52: 0x00]
Minimum Write Performance for 4bit:
 [MIN_PERF_W_4_26: 0x00]
 [MIN_PERF_R_4_26: 0x00]
Power classes registers:
 [PWR_CL_26_360: 0x00]
 [PWR_CL_52_360: 0x00]
 [PWR_CL_26_195: 0x00]
 [PWR_CL_52_195: 0x00]
Partition switching timing [PARTITION_SWITCH_TIME: 0x0a]
Out-of-interrupt busy timing [OUT_OF_INTERRUPT_TIME: 0x05]
I/O Driver Strength [DRIVER_STRENGTH: 0x1f]
Card Type [CARD_TYPE: 0x57]
 HS400 Dual Data Rate eMMC @200MHz 1.8VI/O
 HS200 Single Data Rate eMMC @200MHz 1.8VI/O
 HS Dual Data Rate eMMC @52MHz 1.8V or 3VI/O
 HS eMMC @52MHz - at rated device voltage(s)
 HS eMMC @26MHz - at rated device voltage(s)
CSD structure version [CSD_STRUCTURE: 0x02]
Command set [CMD_SET: 0x00]
Command set revision [CMD_SET_REV: 0x00]
Power class [POWER_CLASS: 0x00]
High-speed interface timing [HS_TIMING: 0x03]
Enhanced Strobe mode [STROBE_SUPPORT: 0x01]  <-----here
Erased memory content [ERASED_MEM_CONT: 0x00]
Boot configuration bytes [PARTITION_CONFIG: 0x00]
> >
> > $ dmesg | grep mmc
> > [   16.321495] [     T60] mmc0: SDHCI controller on fe2e0000.mmc
> > [fe2e0000.mmc] using ADMA
> > [   16.425317] [     T72] mmc0: new HS400 Enhanced strobe MMC card at
> > address 0001
> > [   16.449670] [     T72] mmcblk0: mmc0:0001 SLD64G 57.6 GiB
> > [   16.550133] [     T72]  mmcblk0: p1 p2
> > [   16.577289] [     T72] mmcblk0boot0: mmc0:0001 SLD64G 4.00 MiB
> > [   16.641182] [     T72] mmcblk0boot1: mmc0:0001 SLD64G 4.00 MiB
> > [   16.699865] [     T72] mmcblk0rpmb: mmc0:0001 SLD64G 4.00 MiB,
> > chardev (234:0)
> >
> >> HS400ES for Rockchip platform has been supported for 3 years..
> >>
> > The only modification made was to enable the strobe bit in the eMMC control.
>
> sdhci_dwcmshc_rk35xx_ops->dwcmshc_set_uhs_signaling（） set it... please
> check the code.
>
Ok, I will check this.
> >> please see commit c6f361cba51c536e7a6af31973c6a4e5d7e4e2e4
> >>
> > Based on my analysis and the RK3568 TRM, neither the RK3566 nor the
> > RK2568 supports
> > HS200 or HS400 modes.
>
> There is no a chip called RK2568, so I assume you meant RK3568?
Typo needs to check my eyesight.
> RK3566/RK3568 support HS200, but not HS400（HS400ES also）, so we didn't
> add properties in the DT. This is not because of the code, but the
> chip design reason.
>
Ok understood.

Thanks
-Anand