* [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210
@ 2026-03-11 9:45 Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC Kathiravan Thirumoorthy
` (10 more replies)
0 siblings, 11 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
The IPQ5210 is Qualcomm's SoC for Routers, Gateways and Access Points. This
series adds minimal board boot support for ipq5210-rdp504 board.
SoCs based on IPQ5210 is shipped under 2 different marketing names such as
Qualcomm Dragonwing F8 and Qualcomm Dragonwing N8. The difference being is
F8 parts has the Passive Optical Network(PON) interface which acts as the
backhaul where as in N8 parts it is ethernet backhaul.
Qualcomm Dragonwing F8 Platform:
https://www.qualcomm.com/networking-infrastructure/products/f-series/f8-platform
Qualcomm Dragonwing N8 Platform:
https://www.qualcomm.com/networking-infrastructure/products/n-series/n8-platform
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Kathiravan Thirumoorthy (9):
dt-bindings: clock: add Qualcomm IPQ5210 GCC
clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC
dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
pinctrl: qcom: Introduce IPQ5210 TLMM driver
dt-bindings: qcom: add ipq5210 boards
dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible
dt-bindings: firmware: qcom,scm: Document ipq5210 SCM
arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
arm64: defconfig: enable IPQ5210 RDP504 base configs
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +
.../bindings/clock/qcom,ipq5210-gcc.yaml | 62 +
.../devicetree/bindings/firmware/qcom,scm.yaml | 1 +
.../devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 ++
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 +++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5210.c | 2641 ++++++++++++++++++++
drivers/pinctrl/qcom/Kconfig.msm | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5210.c | 1156 +++++++++
include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 +
include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +
17 files changed, 4678 insertions(+)
---
base-commit: 7109a2155340cc7b21f27e832ece6df03592f2e8
change-id: 20260309-ipq5210_boot_to_shell-43db656579f0
Best regards,
--
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:22 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC Kathiravan Thirumoorthy
` (9 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Add binding for the Qualcomm IPQ5210 Global Clock Controller.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
.../bindings/clock/qcom,ipq5210-gcc.yaml | 62 ++++++++++
include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 ++++++++++++++++++++
include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++++++
3 files changed, 315 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..aeb5d9a3f8322d5d36d2fd19a1d23b275efc34b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5210
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ5210
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq5210-gcc.h
+ include/dt-bindings/reset/qcom,ipq5210-gcc.h
+
+properties:
+ compatible:
+ const: qcom,ipq5210-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE30 PHY0 pipe clock source
+ - description: PCIE30 PHY1 pipe clock source
+ - description: USB3 PHY pipe clock source
+ - description: NSS common clock source
+
+ '#power-domain-cells': false
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,ipq5210-gcc";
+ reg = <0x01800000 0x40000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+ <&pcie30_phy0_pipe_clk>,
+ <&pcie30_phy1_pipe_clk>,
+ <&usb3phy_0_cc_pipe_clk>,
+ <&nss_cmn_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bindings/clock/qcom,ipq5210-gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..84116f34ee4d0433a092987e8d189c2aa95da204
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
+
+#define GCC_ADSS_PWM_CLK 0
+#define GCC_ADSS_PWM_CLK_SRC 1
+#define GCC_CMN_12GPLL_AHB_CLK 2
+#define GCC_CMN_12GPLL_SYS_CLK 3
+#define GCC_CNOC_LPASS_CFG_CLK 4
+#define GCC_CNOC_PCIE0_1LANE_S_CLK 5
+#define GCC_CNOC_PCIE1_2LANE_S_CLK 6
+#define GCC_CNOC_USB_CLK 7
+#define GCC_GEPHY_SYS_CLK 8
+#define GCC_LPASS_AXIM_CLK_SRC 9
+#define GCC_LPASS_CORE_AXIM_CLK 10
+#define GCC_LPASS_SWAY_CLK 11
+#define GCC_LPASS_SWAY_CLK_SRC 12
+#define GCC_MDIO_AHB_CLK 13
+#define GCC_MDIO_GEPHY_AHB_CLK 14
+#define GCC_NSS_TS_CLK 15
+#define GCC_NSS_TS_CLK_SRC 16
+#define GCC_NSSCC_CLK 17
+#define GCC_NSSCFG_CLK 18
+#define GCC_NSSNOC_ATB_CLK 19
+#define GCC_NSSNOC_MEMNOC_1_CLK 20
+#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21
+#define GCC_NSSNOC_MEMNOC_CLK 22
+#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23
+#define GCC_NSSNOC_NSSCC_CLK 24
+#define GCC_NSSNOC_PCNOC_1_CLK 25
+#define GCC_NSSNOC_QOSGEN_REF_CLK 26
+#define GCC_NSSNOC_SNOC_1_CLK 27
+#define GCC_NSSNOC_SNOC_CLK 28
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 29
+#define GCC_NSSNOC_XO_DCD_CLK 30
+#define GCC_PCIE0_AHB_CLK 31
+#define GCC_PCIE0_AUX_CLK 32
+#define GCC_PCIE0_AXI_M_CLK 33
+#define GCC_PCIE0_AXI_M_CLK_SRC 34
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35
+#define GCC_PCIE0_AXI_S_CLK 36
+#define GCC_PCIE0_AXI_S_CLK_SRC 37
+#define GCC_PCIE0_PIPE_CLK 38
+#define GCC_PCIE0_PIPE_CLK_SRC 39
+#define GCC_PCIE0_RCHNG_CLK 40
+#define GCC_PCIE0_RCHNG_CLK_SRC 41
+#define GCC_PCIE1_AHB_CLK 42
+#define GCC_PCIE1_AUX_CLK 43
+#define GCC_PCIE1_AXI_M_CLK 44
+#define GCC_PCIE1_AXI_M_CLK_SRC 45
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46
+#define GCC_PCIE1_AXI_S_CLK 47
+#define GCC_PCIE1_AXI_S_CLK_SRC 48
+#define GCC_PCIE1_PIPE_CLK 49
+#define GCC_PCIE1_PIPE_CLK_SRC 50
+#define GCC_PCIE1_RCHNG_CLK 51
+#define GCC_PCIE1_RCHNG_CLK_SRC 52
+#define GCC_PCIE_AUX_CLK_SRC 53
+#define GCC_PCNOC_BFDCD_CLK_SRC 54
+#define GCC_PON_APB_CLK 55
+#define GCC_PON_TM_CLK 56
+#define GCC_PON_TM2X_CLK 57
+#define GCC_PON_TM2X_CLK_SRC 58
+#define GCC_QDSS_AT_CLK 59
+#define GCC_QDSS_AT_CLK_SRC 60
+#define GCC_QDSS_DAP_CLK 61
+#define GCC_QDSS_TSCTR_CLK_SRC 62
+#define GCC_QPIC_AHB_CLK 63
+#define GCC_QPIC_CLK 64
+#define GCC_QPIC_CLK_SRC 65
+#define GCC_QPIC_IO_MACRO_CLK 66
+#define GCC_QPIC_IO_MACRO_CLK_SRC 67
+#define GCC_QRNG_AHB_CLK 68
+#define GCC_QUPV3_AHB_MST_CLK 69
+#define GCC_QUPV3_AHB_SLV_CLK 70
+#define GCC_QUPV3_WRAP_SE0_CLK 71
+#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72
+#define GCC_QUPV3_WRAP_SE1_CLK 73
+#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74
+#define GCC_QUPV3_WRAP_SE2_CLK 75
+#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76
+#define GCC_QUPV3_WRAP_SE3_CLK 77
+#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78
+#define GCC_QUPV3_WRAP_SE4_CLK 79
+#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80
+#define GCC_QUPV3_WRAP_SE5_CLK 81
+#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82
+#define GCC_SDCC1_AHB_CLK 83
+#define GCC_SDCC1_APPS_CLK 84
+#define GCC_SDCC1_APPS_CLK_SRC 85
+#define GCC_SDCC1_ICE_CORE_CLK 86
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 87
+#define GCC_SLEEP_CLK_SRC 88
+#define GCC_SNOC_LPASS_CLK 89
+#define GCC_SNOC_PCIE0_AXI_M_CLK 90
+#define GCC_SNOC_PCIE1_AXI_M_CLK 91
+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92
+#define GCC_UNIPHY0_AHB_CLK 93
+#define GCC_UNIPHY0_SYS_CLK 94
+#define GCC_UNIPHY1_AHB_CLK 95
+#define GCC_UNIPHY1_SYS_CLK 96
+#define GCC_UNIPHY2_AHB_CLK 97
+#define GCC_UNIPHY2_SYS_CLK 98
+#define GCC_UNIPHY_SYS_CLK_SRC 99
+#define GCC_USB0_AUX_CLK 100
+#define GCC_USB0_AUX_CLK_SRC 101
+#define GCC_USB0_MASTER_CLK 102
+#define GCC_USB0_MASTER_CLK_SRC 103
+#define GCC_USB0_MOCK_UTMI_CLK 104
+#define GCC_USB0_MOCK_UTMI_CLK_SRC 105
+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106
+#define GCC_USB0_PHY_CFG_AHB_CLK 107
+#define GCC_USB0_PIPE_CLK 108
+#define GCC_USB0_PIPE_CLK_SRC 109
+#define GCC_USB0_SLEEP_CLK 110
+#define GCC_XO_CLK_SRC 111
+#define GPLL0_MAIN 112
+#define GPLL0 113
+#define GPLL2_MAIN 114
+#define GPLL2 115
+#define GPLL4_MAIN 116
+#endif
diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bindings/reset/qcom,ipq5210-gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..09890a09087c39288683d105437fc68f3d68be4c
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
+
+#define GCC_ADSS_BCR 0
+#define GCC_ADSS_PWM_ARES 1
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3
+#define GCC_APSS_AHB_ARES 4
+#define GCC_APSS_ATB_ARES 5
+#define GCC_APSS_AXI_ARES 6
+#define GCC_APSS_TS_ARES 7
+#define GCC_BOOT_ROM_AHB_ARES 8
+#define GCC_BOOT_ROM_BCR 9
+#define GCC_GEPHY_BCR 10
+#define GCC_GEPHY_SYS_ARES 11
+#define GCC_GP1_ARES 12
+#define GCC_GP2_ARES 13
+#define GCC_GP3_ARES 14
+#define GCC_MDIO_AHB_ARES 15
+#define GCC_MDIO_BCR 16
+#define GCC_MDIO_GEPHY_AHB_ARES 17
+#define GCC_NSS_BCR 18
+#define GCC_NSS_TS_ARES 19
+#define GCC_NSSCC_ARES 20
+#define GCC_NSSCFG_ARES 21
+#define GCC_NSSNOC_ATB_ARES 22
+#define GCC_NSSNOC_MEMNOC_1_ARES 23
+#define GCC_NSSNOC_MEMNOC_ARES 24
+#define GCC_NSSNOC_NSSCC_ARES 25
+#define GCC_NSSNOC_PCNOC_1_ARES 26
+#define GCC_NSSNOC_QOSGEN_REF_ARES 27
+#define GCC_NSSNOC_SNOC_1_ARES 28
+#define GCC_NSSNOC_SNOC_ARES 29
+#define GCC_NSSNOC_TIMEOUT_REF_ARES 30
+#define GCC_NSSNOC_XO_DCD_ARES 31
+#define GCC_PCIE0_AHB_ARES 32
+#define GCC_PCIE0_AUX_ARES 33
+#define GCC_PCIE0_AXI_M_ARES 34
+#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35
+#define GCC_PCIE0_AXI_S_ARES 36
+#define GCC_PCIE0_BCR 37
+#define GCC_PCIE0_LINK_DOWN_BCR 38
+#define GCC_PCIE0_PHY_BCR 39
+#define GCC_PCIE0_PIPE_ARES 40
+#define GCC_PCIE0PHY_PHY_BCR 41
+#define GCC_PCIE1_AHB_ARES 42
+#define GCC_PCIE1_AUX_ARES 43
+#define GCC_PCIE1_AXI_M_ARES 44
+#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45
+#define GCC_PCIE1_AXI_S_ARES 46
+#define GCC_PCIE1_BCR 47
+#define GCC_PCIE1_LINK_DOWN_BCR 48
+#define GCC_PCIE1_PHY_BCR 49
+#define GCC_PCIE1_PIPE_ARES 50
+#define GCC_PCIE1PHY_PHY_BCR 51
+#define GCC_QRNG_AHB_ARES 52
+#define GCC_QRNG_BCR 53
+#define GCC_QUPV3_2X_CORE_ARES 54
+#define GCC_QUPV3_AHB_MST_ARES 55
+#define GCC_QUPV3_AHB_SLV_ARES 56
+#define GCC_QUPV3_BCR 57
+#define GCC_QUPV3_CORE_ARES 58
+#define GCC_QUPV3_WRAP_SE0_ARES 59
+#define GCC_QUPV3_WRAP_SE0_BCR 60
+#define GCC_QUPV3_WRAP_SE1_ARES 61
+#define GCC_QUPV3_WRAP_SE1_BCR 62
+#define GCC_QUPV3_WRAP_SE2_ARES 63
+#define GCC_QUPV3_WRAP_SE2_BCR 64
+#define GCC_QUPV3_WRAP_SE3_ARES 65
+#define GCC_QUPV3_WRAP_SE3_BCR 66
+#define GCC_QUPV3_WRAP_SE4_ARES 67
+#define GCC_QUPV3_WRAP_SE4_BCR 68
+#define GCC_QUPV3_WRAP_SE5_ARES 69
+#define GCC_QUPV3_WRAP_SE5_BCR 70
+#define GCC_QUSB2_0_PHY_BCR 71
+#define GCC_SDCC1_AHB_ARES 72
+#define GCC_SDCC1_APPS_ARES 73
+#define GCC_SDCC1_ICE_CORE_ARES 74
+#define GCC_SDCC_BCR 75
+#define GCC_TLMM_AHB_ARES 76
+#define GCC_TLMM_ARES 77
+#define GCC_TLMM_BCR 78
+#define GCC_UNIPHY0_AHB_ARES 79
+#define GCC_UNIPHY0_BCR 80
+#define GCC_UNIPHY0_SYS_ARES 81
+#define GCC_UNIPHY1_AHB_ARES 82
+#define GCC_UNIPHY1_BCR 83
+#define GCC_UNIPHY1_SYS_ARES 84
+#define GCC_UNIPHY2_AHB_ARES 85
+#define GCC_UNIPHY2_BCR 86
+#define GCC_UNIPHY2_SYS_ARES 87
+#define GCC_USB0_AUX_ARES 88
+#define GCC_USB0_MASTER_ARES 89
+#define GCC_USB0_MOCK_UTMI_ARES 90
+#define GCC_USB0_PHY_BCR 91
+#define GCC_USB0_PHY_CFG_AHB_ARES 92
+#define GCC_USB0_PIPE_ARES 93
+#define GCC_USB0_SLEEP_ARES 94
+#define GCC_USB3PHY_0_PHY_BCR 95
+#define GCC_USB_BCR 96
+#define GCC_PCIE0_PIPE_RESET 97
+#define GCC_PCIE0_CORE_STICKY_RESET 98
+#define GCC_PCIE0_AXI_S_STICKY_RESET 99
+#define GCC_PCIE0_AXI_S_RESET 100
+#define GCC_PCIE0_AXI_M_STICKY_RESET 101
+#define GCC_PCIE0_AXI_M_RESET 102
+#define GCC_PCIE0_AUX_RESET 103
+#define GCC_PCIE0_AHB_RESET 104
+#define GCC_PCIE1_PIPE_RESET 105
+#define GCC_PCIE1_CORE_STICKY_RESET 106
+#define GCC_PCIE1_AXI_S_STICKY_RESET 107
+#define GCC_PCIE1_AXI_S_RESET 108
+#define GCC_PCIE1_AXI_M_STICKY_RESET 109
+#define GCC_PCIE1_AXI_M_RESET 110
+#define GCC_PCIE1_AUX_RESET 111
+#define GCC_PCIE1_AHB_RESET 112
+#define GCC_UNIPHY0_XPCS_ARES 113
+#define GCC_UNIPHY1_XPCS_ARES 114
+#define GCC_UNIPHY2_XPCS_ARES 115
+#define GCC_QDSS_BCR 116
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-11 14:50 ` Dmitry Baryshkov
2026-03-11 9:45 ` [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Kathiravan Thirumoorthy
` (8 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Add support for the global clock controller found on IPQ5210 SoC.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5210.c | 2641 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 2650 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index f23280219d56436fd142a38ff22a219e431539a6..171cb4a6198b1a70a958bc0dfbdd7b65cdaa7bea 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -332,6 +332,14 @@ config IPQ_GCC_5018
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_GCC_5210
+ tristate "IPQ5210 Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for the global clock controller on ipq5210 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
config IPQ_GCC_5332
tristate "IPQ5332 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 90ea21c3b7cf7956309648c4445ecf8fd61f23b0..c07214c0dd83f43e7847ae374957bf6536cc3451 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
+obj-$(CONFIG_IPQ_GCC_5210) += gcc-ipq5210.o
obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
obj-$(CONFIG_IPQ_GCC_5424) += gcc-ipq5424.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
diff --git a/drivers/clk/qcom/gcc-ipq5210.c b/drivers/clk/qcom/gcc-ipq5210.c
new file mode 100644
index 0000000000000000000000000000000000000000..3294a6e116ea984e256e75e9d70b39a75d685d54
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq5210.c
@@ -0,0 +1,2641 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "reset.h"
+
+enum {
+ DT_XO,
+ DT_SLEEP_CLK,
+ DT_PCIE30_PHY0_PIPE_CLK,
+ DT_PCIE30_PHY1_PIPE_CLK,
+ DT_USB3_PHY0_CC_PIPE_CLK,
+ DT_NSS_CMN_CLK,
+};
+
+enum {
+ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
+ P_GPLL0_OUT_AUX,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL2_OUT_AUX,
+ P_GPLL2_OUT_MAIN,
+ P_GPLL4_OUT_AUX,
+ P_GPLL4_OUT_MAIN,
+ P_NSS_CMN_CLK,
+ P_SLEEP_CLK,
+ P_USB3PHY_0_PIPE,
+ P_XO,
+};
+
+static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_main",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_div2",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll0",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll2_main",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gpll2[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x21000,
+ .post_div_table = post_div_table_gpll2,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll2),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll2",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll2_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll4_main",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+static const struct parent_map gcc_parent_map_xo[] = {
+ { P_XO, 0 },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL4_OUT_MAIN, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4_main.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_XO, 0 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+ { P_XO, 0 },
+ { P_NSS_CMN_CLK, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_GPLL2_OUT_AUX, 3 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .index = DT_XO },
+ { .index = DT_NSS_CMN_CLK },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2_main.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_MAIN, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL4_OUT_MAIN, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_7[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4_main.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_8[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_8[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_9[] = {
+ { P_XO, 0 },
+ { P_GPLL4_OUT_AUX, 1 },
+ { P_GPLL0_OUT_MAIN, 3 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_9[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4_main.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_10[] = {
+ { P_XO, 0 },
+ { P_GPLL4_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_10[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4_main.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_11[] = {
+ { P_XO, 0 },
+ { P_GPLL4_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_11[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4_main.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_12[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_12[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2_main.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_13[] = {
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_13[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_adss_pwm_clk_src = {
+ .cmd_rcgr = 0x1c004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_adss_pwm_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_nss_ts_clk_src = {
+ .cmd_rcgr = 0x17088,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nss_ts_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x2e004,
+ .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_7,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_system_noc_bfdcd_clk_src",
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] = {
+ F(429000000, P_NSS_CMN_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x17004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_memnoc_bfdcd_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = {
+ F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = {
+ .cmd_rcgr = 0x28018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_axi_m_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie0_rchng_clk_src = {
+ .cmd_rcgr = 0x28028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_rchng_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] = {
+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = {
+ .cmd_rcgr = 0x29018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_axi_m_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = {
+ .cmd_rcgr = 0x29020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie1_rchng_clk_src = {
+ .cmd_rcgr = 0x29028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_rchng_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
+ F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_aux_clk_src = {
+ .cmd_rcgr = 0x28004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_5,
+ .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_aux_clk_src",
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] = {
+ F(960000, P_XO, 10, 2, 5),
+ F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217),
+ F(4800000, P_XO, 5, 0, 0),
+ F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217),
+ F(9600000, P_XO, 2.5, 0, 0),
+ F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217),
+ F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
+ F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
+ F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
+ F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250),
+ F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+ F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
+ F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
+ F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217),
+ F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
+ F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src = {
+ .cmd_rcgr = 0x4004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se0_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src = {
+ .cmd_rcgr = 0x5004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se1_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src = {
+ .cmd_rcgr = 0x2018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src = {
+ .cmd_rcgr = 0x2034,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se3_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src = {
+ .cmd_rcgr = 0x3018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se4_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src = {
+ .cmd_rcgr = 0x3034,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se5_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 12, 125),
+ F(400000, P_XO, 12, 1, 5),
+ F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
+ F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
+ F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+ F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x33004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_6,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
+ F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x33018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_7,
+ .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ice_core_clk_src",
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
+ .cmd_rcgr = 0x17090,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy_sys_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb0_aux_clk_src = {
+ .cmd_rcgr = 0x2c018,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_aux_clk_src",
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = {
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb0_master_clk_src = {
+ .cmd_rcgr = 0x2c004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb0_master_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
+ F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2c02c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_9,
+ .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
+ F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qdss_at_clk_src = {
+ .cmd_rcgr = 0x2d004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_10,
+ .freq_tbl = ftbl_gcc_qdss_at_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qdss_at_clk_src",
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
+ F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
+ .cmd_rcgr = 0x2d01c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_10,
+ .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qdss_tsctr_clk_src",
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x31004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcnoc_bfdcd_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
+ .cmd_rcgr = 0x32004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_12,
+ .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qpic_io_macro_clk_src",
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qpic_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qpic_clk_src = {
+ .cmd_rcgr = 0x32020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_12,
+ .freq_tbl = ftbl_gcc_qpic_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qpic_clk_src",
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pon_tm2x_clk_src[] = {
+ F(342860000, P_GPLL4_OUT_MAIN, 3.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pon_tm2x_clk_src = {
+ .cmd_rcgr = 0x3c004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_11,
+ .freq_tbl = ftbl_gcc_pon_tm2x_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pon_tm2x_clk_src",
+ .parent_data = gcc_parent_data_11,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
+ F(32000, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sleep_clk_src = {
+ .cmd_rcgr = 0x3400c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_13,
+ .freq_tbl = ftbl_gcc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sleep_clk_src",
+ .parent_data = gcc_parent_data_13,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_13),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_lpass_sway_clk_src = {
+ .cmd_rcgr = 0x27004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_lpass_sway_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_lpass_axim_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_lpass_axim_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src = {
+ .reg = 0x1700c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_memnoc_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
+ .reg = 0x2c040,
+ .shift = 0,
+ .width = 2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb0_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_pon_tm_div_clk_src = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pon_tm_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_pon_tm2x_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+ .halt_reg = 0x1c00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_adss_pwm_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_adss_pwm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = {
+ .halt_reg = 0x31088,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31088,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cnoc_pcie0_1lane_s_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cnoc_pcie1_2lane_s_clk = {
+ .halt_reg = 0x3108c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3108c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cnoc_pcie1_2lane_s_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cnoc_usb_clk = {
+ .halt_reg = 0x310a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x310a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cnoc_usb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_ahb_clk = {
+ .halt_reg = 0x17040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_mdio_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_gephy_ahb_clk = {
+ .halt_reg = 0x17098,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17098,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_mdio_gephy_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ts_clk = {
+ .halt_reg = 0x17018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nss_ts_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_nss_ts_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nsscc_clk = {
+ .halt_reg = 0x17034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nsscc_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nsscfg_clk = {
+ .halt_reg = 0x1702c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1702c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nsscfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_atb_clk = {
+ .halt_reg = 0x17014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_atb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_memnoc_1_clk = {
+ .halt_reg = 0x17084,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17084,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_memnoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_nssnoc_memnoc_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_memnoc_clk = {
+ .halt_reg = 0x17024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_memnoc_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_nssnoc_memnoc_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_nsscc_clk = {
+ .halt_reg = 0x17030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_nsscc_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 gcc_xo_clk_src = {
+ .cmd_rcgr = 0x34004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_xo_clk_src",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_xo_div4_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_branch gcc_gephy_sys_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gephy_sys_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
+ .halt_reg = 0x17080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_pcnoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
+ .halt_reg = 0x1701c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_qosgen_ref_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_div4_clk_src.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_1_clk = {
+ .halt_reg = 0x1707c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1707c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_snoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_clk = {
+ .halt_reg = 0x17028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_snoc_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
+ .halt_reg = 0x17020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_timeout_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_xo_div4_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
+ .halt_reg = 0x17074,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_nssnoc_xo_dcd_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_ahb_clk = {
+ .halt_reg = 0x28030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+ .halt_reg = 0x28070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+ .halt_reg = 0x28038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie0_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+ .halt_reg = 0x28048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+ .halt_reg = 0x28040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = {
+ .reg = 0x28064,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "pcie0_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_PCIE30_PHY0_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+ .halt_reg = 0x29030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+ .halt_reg = 0x29074,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+ .halt_reg = 0x29038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie1_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
+ .halt_reg = 0x29048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+ .halt_reg = 0x29040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = {
+ .reg = 0x29064,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "pcie1_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_PCIE30_PHY1_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x29068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_pcie1_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qrng_ahb_clk = {
+ .halt_reg = 0x13024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qrng_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_ahb_mst_clk = {
+ .halt_reg = 0x1014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_ahb_mst_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_ahb_slv_clk = {
+ .halt_reg = 0x102c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_ahb_slv_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se0_clk = {
+ .halt_reg = 0x4020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se1_clk = {
+ .halt_reg = 0x5020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se2_clk = {
+ .halt_reg = 0x202c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x202c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se3_clk = {
+ .halt_reg = 0x2048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se4_clk = {
+ .halt_reg = 0x302c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_se5_clk = {
+ .halt_reg = 0x3048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_se5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap_se5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x3303c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3303c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x3302c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x33034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sdcc1_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie0_axi_m_clk = {
+ .halt_reg = 0x2e04c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_snoc_pcie0_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie0_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie1_axi_m_clk = {
+ .halt_reg = 0x2e050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_snoc_pcie1_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie1_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_ahb_clk = {
+ .halt_reg = 0x1704c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1704c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_sys_clk = {
+ .halt_reg = 0x17048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy0_sys_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_ahb_clk = {
+ .halt_reg = 0x1705c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1705c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_sys_clk = {
+ .halt_reg = 0x17058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy1_sys_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_ahb_clk = {
+ .halt_reg = 0x1706c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1706c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy2_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_sys_clk = {
+ .halt_reg = 0x17068,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_uniphy2_sys_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x2c04c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x2c044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x2c050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x2c05c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c05c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
+ .reg = 0x2c074,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_USB3_PHY0_CC_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_rchng_clk = {
+ .halt_reg = 0x28028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28028,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_rchng_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_pcie0_rchng_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_rchng_clk = {
+ .halt_reg = 0x29028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29028,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_rchng_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_pcie1_rchng_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x32010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x32010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qpic_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x32028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x32028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qpic_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qpic_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_io_macro_clk = {
+ .halt_reg = 0x3200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qpic_io_macro_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qpic_io_macro_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
+ .halt_reg = 0x3a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cmn_12gpll_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
+ .halt_reg = 0x3a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cmn_12gpll_sys_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x2d034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2d034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qdss_at_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x2d058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qdss_dap_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pon_apb_clk = {
+ .halt_reg = 0x3c01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3c01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pon_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pon_tm_clk = {
+ .halt_reg = 0x3c014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3c014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pon_tm_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pon_tm_div_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pon_tm2x_clk = {
+ .halt_reg = 0x3c00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3c00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pon_tm2x_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pon_tm2x_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_clk = {
+ .halt_reg = 0x2e028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_snoc_lpass_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x27014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cnoc_lpass_cfg_clk = {
+ .halt_reg = 0x31020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cnoc_lpass_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_core_axim_clk = {
+ .halt_reg = 0x27018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_lpass_core_axim_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static __maybe_unused struct clk_regmap *gcc_ipq5210_clocks[] = {
+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
+ [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
+ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
+ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
+ [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr,
+ [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr,
+ [GCC_CNOC_PCIE1_2LANE_S_CLK] = &gcc_cnoc_pcie1_2lane_s_clk.clkr,
+ [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr,
+ [GCC_GEPHY_SYS_CLK] = &gcc_gephy_sys_clk.clkr,
+ [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr,
+ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
+ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
+ [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
+ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+ [GCC_MDIO_GEPHY_AHB_CLK] = &gcc_mdio_gephy_ahb_clk.clkr,
+ [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
+ [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
+ [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
+ [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
+ [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
+ [GCC_NSSNOC_MEMNOC_1_CLK] = &gcc_nssnoc_memnoc_1_clk.clkr,
+ [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr,
+ [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
+ [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] = &gcc_nssnoc_memnoc_div_clk_src.clkr,
+ [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
+ [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
+ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
+ [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
+ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
+ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
+ [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr,
+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr,
+ [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
+ [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr,
+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr,
+ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
+ [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr,
+ [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
+ [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
+ [GCC_PON_APB_CLK] = &gcc_pon_apb_clk.clkr,
+ [GCC_PON_TM_CLK] = &gcc_pon_tm_clk.clkr,
+ [GCC_PON_TM2X_CLK] = &gcc_pon_tm2x_clk.clkr,
+ [GCC_PON_TM2X_CLK_SRC] = &gcc_pon_tm2x_clk_src.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr,
+ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
+ [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
+ [GCC_QRNG_AHB_CLK] = &gcc_qrng_ahb_clk.clkr,
+ [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr,
+ [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr,
+ [GCC_QUPV3_WRAP_SE0_CLK] = &gcc_qupv3_wrap_se0_clk.clkr,
+ [GCC_QUPV3_WRAP_SE0_CLK_SRC] = &gcc_qupv3_wrap_se0_clk_src.clkr,
+ [GCC_QUPV3_WRAP_SE1_CLK] = &gcc_qupv3_wrap_se1_clk.clkr,
+ [GCC_QUPV3_WRAP_SE1_CLK_SRC] = &gcc_qupv3_wrap_se1_clk_src.clkr,
+ [GCC_QUPV3_WRAP_SE2_CLK] = &gcc_qupv3_wrap_se2_clk.clkr,
+ [GCC_QUPV3_WRAP_SE2_CLK_SRC] = &gcc_qupv3_wrap_se2_clk_src.clkr,
+ [GCC_QUPV3_WRAP_SE3_CLK] = &gcc_qupv3_wrap_se3_clk.clkr,
+ [GCC_QUPV3_WRAP_SE3_CLK_SRC] = &gcc_qupv3_wrap_se3_clk_src.clkr,
+ [GCC_QUPV3_WRAP_SE4_CLK] = &gcc_qupv3_wrap_se4_clk.clkr,
+ [GCC_QUPV3_WRAP_SE4_CLK_SRC] = &gcc_qupv3_wrap_se4_clk_src.clkr,
+ [GCC_QUPV3_WRAP_SE5_CLK] = &gcc_qupv3_wrap_se5_clk.clkr,
+ [GCC_QUPV3_WRAP_SE5_CLK_SRC] = &gcc_qupv3_wrap_se5_clk_src.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr,
+ [GCC_SNOC_PCIE0_AXI_M_CLK] = &gcc_snoc_pcie0_axi_m_clk.clkr,
+ [GCC_SNOC_PCIE1_AXI_M_CLK] = &gcc_snoc_pcie1_axi_m_clk.clkr,
+ [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
+ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
+ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
+ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
+ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
+ [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
+ [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
+ [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
+ [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq5210_resets[] = {
+ [GCC_ADSS_BCR] = { 0x1c000 },
+ [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES] = { 0x3800c, 2 },
+ [GCC_APSS_AHB_ARES] = { 0x24014, 2 },
+ [GCC_APSS_ATB_ARES] = { 0x24034, 2 },
+ [GCC_APSS_AXI_ARES] = { 0x24018, 2 },
+ [GCC_APSS_TS_ARES] = { 0x24030, 2 },
+ [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 },
+ [GCC_BOOT_ROM_BCR] = { 0x13028 },
+ [GCC_GEPHY_BCR] = { 0x2a000 },
+ [GCC_GEPHY_SYS_ARES] = { 0x2a004, 2 },
+ [GCC_GP1_ARES] = { 0x8018, 2 },
+ [GCC_GP2_ARES] = { 0x9018, 2 },
+ [GCC_GP3_ARES] = { 0xa018, 2 },
+ [GCC_MDIO_AHB_ARES] = { 0x17040, 2 },
+ [GCC_MDIO_BCR] = { 0x1703c },
+ [GCC_MDIO_GEPHY_AHB_ARES] = { 0x17098, 2 },
+ [GCC_NSS_BCR] = { 0x17000 },
+ [GCC_NSS_TS_ARES] = { 0x17018, 2 },
+ [GCC_NSSCC_ARES] = { 0x17034, 2 },
+ [GCC_NSSCFG_ARES] = { 0x1702c, 2 },
+ [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 },
+ [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 },
+ [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 },
+ [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 },
+ [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 },
+ [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 },
+ [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 },
+ [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 },
+ [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 },
+ [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 },
+ [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 },
+ [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 },
+ [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 },
+ [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2 },
+ [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 },
+ [GCC_PCIE0_BCR] = { 0x28000 },
+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054 },
+ [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 },
+ [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 },
+ [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 },
+ [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 },
+ [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 },
+ [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 },
+ [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 },
+ [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 },
+ [GCC_PCIE0_PHY_BCR] = { 0x28060 },
+ [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2 },
+ [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c },
+ [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 },
+ [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 },
+ [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 },
+ [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 },
+ [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 },
+ [GCC_PCIE1_BCR] = { 0x29000 },
+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054 },
+ [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 },
+ [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 },
+ [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 },
+ [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 },
+ [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 },
+ [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 },
+ [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 },
+ [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 },
+ [GCC_PCIE1_PHY_BCR] = { 0x29060 },
+ [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 },
+ [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c },
+ [GCC_QRNG_AHB_ARES] = { 0x13024, 2 },
+ [GCC_QRNG_BCR] = { 0x13020 },
+ [GCC_QUPV3_2X_CORE_ARES] = { 0x1020, 2 },
+ [GCC_QUPV3_AHB_MST_ARES] = { 0x1014, 2 },
+ [GCC_QUPV3_AHB_SLV_ARES] = { 0x102c, 2 },
+ [GCC_QUPV3_BCR] = { 0x1000 },
+ [GCC_QUPV3_CORE_ARES] = { 0x1018, 2 },
+ [GCC_QUPV3_WRAP_SE0_ARES] = { 0x4020, 2 },
+ [GCC_QUPV3_WRAP_SE0_BCR] = { 0x4000 },
+ [GCC_QUPV3_WRAP_SE1_ARES] = { 0x5020, 2 },
+ [GCC_QUPV3_WRAP_SE1_BCR] = { 0x5000 },
+ [GCC_QUPV3_WRAP_SE2_ARES] = { 0x202c, 2 },
+ [GCC_QUPV3_WRAP_SE2_BCR] = { 0x2000 },
+ [GCC_QUPV3_WRAP_SE3_ARES] = { 0x2048, 2 },
+ [GCC_QUPV3_WRAP_SE3_BCR] = { 0x2030 },
+ [GCC_QUPV3_WRAP_SE4_ARES] = { 0x302c, 2 },
+ [GCC_QUPV3_WRAP_SE4_BCR] = { 0x3000 },
+ [GCC_QUPV3_WRAP_SE5_ARES] = { 0x3048, 2 },
+ [GCC_QUPV3_WRAP_SE5_BCR] = { 0x3030 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
+ [GCC_SDCC1_AHB_ARES] = { 0x3303c, 2 },
+ [GCC_SDCC1_APPS_ARES] = { 0x3302c, 2 },
+ [GCC_SDCC1_ICE_CORE_ARES] = { 0x33034, 2 },
+ [GCC_SDCC_BCR] = { 0x33000 },
+ [GCC_TLMM_AHB_ARES] = { 0x3e004, 2 },
+ [GCC_TLMM_ARES] = { 0x3e008, 2 },
+ [GCC_TLMM_BCR] = { 0x3e000 },
+ [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 },
+ [GCC_UNIPHY0_BCR] = { 0x17044 },
+ [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 },
+ [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 },
+ [GCC_UNIPHY1_BCR] = { 0x17054 },
+ [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 },
+ [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 },
+ [GCC_UNIPHY2_BCR] = { 0x17064 },
+ [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 },
+ [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 },
+ [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 },
+ [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 },
+ [GCC_USB0_PHY_BCR] = { 0x2c06c },
+ [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 },
+ [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 },
+ [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 },
+ [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
+ [GCC_USB_BCR] = { 0x2c000 },
+ [GCC_QDSS_BCR] = { 0x2d000 },
+};
+
+static const struct of_device_id gcc_ipq5210_match_table[] = {
+ { .compatible = "qcom,ipq5210-gcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq5210_match_table);
+
+static const struct regmap_config gcc_ipq5210_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x3f024,
+ .fast_io = true,
+};
+
+static struct clk_hw *gcc_ipq5210_hws[] = {
+ &gpll0_div2.hw,
+ &gcc_xo_div4_clk_src.hw,
+ &gcc_pon_tm_div_clk_src.hw,
+};
+
+static const struct qcom_cc_desc gcc_ipq5210_desc = {
+ .config = &gcc_ipq5210_regmap_config,
+ .clks = gcc_ipq5210_clocks,
+ .num_clks = ARRAY_SIZE(gcc_ipq5210_clocks),
+ .resets = gcc_ipq5210_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq5210_resets),
+ .clk_hws = gcc_ipq5210_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_ipq5210_hws),
+};
+
+static int gcc_ipq5210_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &gcc_ipq5210_desc);
+}
+
+static struct platform_driver gcc_ipq5210_driver = {
+ .probe = gcc_ipq5210_probe,
+ .driver = {
+ .name = "qcom,gcc-ipq5210",
+ .of_match_table = gcc_ipq5210_match_table,
+ },
+};
+
+static int __init gcc_ipq5210_init(void)
+{
+ return platform_driver_register(&gcc_ipq5210_driver);
+}
+core_initcall(gcc_ipq5210_init);
+
+static void __exit gcc_ipq5210_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq5210_driver);
+}
+module_exit(gcc_ipq5210_exit);
+
+MODULE_DESCRIPTION("QTI GCC IPQ5210 Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:24 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Kathiravan Thirumoorthy
` (7 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Add device tree bindings for IPQ5210 TLMM block.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
.../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++++++
1 file changed, 141 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b615c67e642152c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5210 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
+
+description: |
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5210-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 27
+
+ gpio-line-names:
+ maxItems: 54
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5210-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5210-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5210-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char_start, atest_char_status0, atest_char_status1,
+ atest_char_status2, atest_char_status3, atest_tic_en, audio_pri0,
+ audio_pri1, audio_pri2, audio_pri3, audio_pri_d0, audio_pri_d1,
+ audio_pri_fsync, audio_pri_pclk, audio_sec0, audio_sec1,
+ audio_sec2, audio_sec3, audio_sec_d0, audio_sec_d1,
+ audio_sec_fsync, audio_sec_pclk, core_voltage_0, cri_trng0,
+ cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
+ gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, Led00,
+ led01, led02, led10, led11, led12, led20, led21, led22,
+ mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, mdio_slv0,
+ mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, pcie0_wake,
+ pcie1_clk_req_n, pcie1_wake, pll_test, pon_active_led,
+ pon_mux_sel, pon_rx, pon_rx_los, pon_tx, pon_tx_burst,
+ pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, gpn_tx_burst,
+ gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm_out00, pwm_out01,
+ pwm_out02, pwm_out03, pwm_out10, pwm_out11, pwm_out12,
+ pwm_out20, pwm_out21, pwm_out22, pwm_out30, pwm_out31,
+ pwm_out32, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
+ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
+ qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
+ qspi_data, qspi_clk, qspi_cs_n, qup_se0_l0, qup_se0_l1,
+ qup_se0_l2, qup_se0_l3, qup_se0_l4, qup_se0_l5, qup_se1_l0,
+ qup_se1_l1, qup_se1_l2, qup_se1_l3, qup_se2_l00, qup_se2_l01,
+ qup_se2_l10, qup_se2_l11, qup_se2_l2, qup_se2_l3, qup_se3_l0,
+ qup_se3_l1, qup_se3_l2, qup_se3_l3, qup_se4_l0, qup_se4_l1,
+ qup_se4_l2, qup_se4_l3, qup_se4_l4, qup_se4_l5, qup_se5_l00,
+ qup_se5_l01, qup_se5_l10, qup_se5_l11, qup_se5_l2, qup_se5_l3,
+ qup_se5_l4, qup_se5_l5, resout, rx_los00, rx_los01, rx_los10,
+ rx_los11, rx_los20, rx_los21, sdc_clk, sdc_cmd, sdc_data,
+ tsens_max ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5210-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ gpio-ranges = <&tlmm 0 0 54>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ qup-uart1-default-state {
+ tx-pins {
+ pins = "gpio39";
+ function = "qup_se1_l2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ rx-pins {
+ pins = "gpio38";
+ function = "qup_se1_l3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+ };
+
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (2 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-11 14:45 ` Dmitry Baryshkov
2026-03-13 12:54 ` Konrad Dybcio
2026-03-11 9:45 ` [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards Kathiravan Thirumoorthy
` (6 subsequent siblings)
10 siblings, 2 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
so add a driver for it.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
drivers/pinctrl/qcom/Kconfig.msm | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5210.c | 1156 ++++++++++++++++++++++++++++++++
3 files changed, 1165 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm
index 6df6159fa5f89f9f0470e700b4698dc8849ed515..17416dce8e70cce022c6ffdc2d3ac8adf7aae1ff 100644
--- a/drivers/pinctrl/qcom/Kconfig.msm
+++ b/drivers/pinctrl/qcom/Kconfig.msm
@@ -58,6 +58,14 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
+config PINCTRL_IPQ5210
+ tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver"
+ depends on ARM64 || COMPILE_TEST
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc IPQ5210 platform.
+
config PINCTRL_IPQ5332
tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index a8fd12f90d6e6f8e139097cc0a81d6f178f09000..84ff95ff246a4073508d60e92a09f82f989bb50f 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ5210) += pinctrl-ipq5210.o
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/pinctrl-ipq5210.c
new file mode 100644
index 0000000000000000000000000000000000000000..182bfeae6b30f79ed289cbe3c2d6ba8bb28705f8
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-msm.h"
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .grp = PINCTRL_PINGROUP("gpio" #id, \
+ gpio##id##_pins, \
+ ARRAY_SIZE(gpio##id##_pins)), \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9, \
+ }, \
+ .nfuncs = 10, \
+ }
+
+static const struct pinctrl_pin_desc ipq5210_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+
+enum ipq5210_functions {
+ msm_mux_atest_char_start,
+ msm_mux_atest_char_status0,
+ msm_mux_atest_char_status1,
+ msm_mux_atest_char_status2,
+ msm_mux_atest_char_status3,
+ msm_mux_atest_tic_en,
+ msm_mux_audio_pri0,
+ msm_mux_audio_pri1,
+ msm_mux_audio_pri2,
+ msm_mux_audio_pri3,
+ msm_mux_audio_pri_d0,
+ msm_mux_audio_pri_d1,
+ msm_mux_audio_pri_fsync,
+ msm_mux_audio_pri_pclk,
+ msm_mux_audio_sec0,
+ msm_mux_audio_sec1,
+ msm_mux_audio_sec2,
+ msm_mux_audio_sec3,
+ msm_mux_audio_sec_d0,
+ msm_mux_audio_sec_d1,
+ msm_mux_audio_sec_fsync,
+ msm_mux_audio_sec_pclk,
+ msm_mux_core_voltage_0,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cri_trng2,
+ msm_mux_cri_trng3,
+ msm_mux_dbg_out_clk,
+ msm_mux_dg_out,
+ msm_mux_gcc_plltest_bypassnl,
+ msm_mux_gcc_plltest_resetn,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_Led00,
+ msm_mux_led01,
+ msm_mux_led02,
+ msm_mux_led10,
+ msm_mux_led11,
+ msm_mux_led12,
+ msm_mux_led20,
+ msm_mux_led21,
+ msm_mux_led22,
+ msm_mux_mdc_mst,
+ msm_mux_mdc_slv0,
+ msm_mux_mdc_slv1,
+ msm_mux_mdc_slv2,
+ msm_mux_mdio_mst,
+ msm_mux_mdio_slv0,
+ msm_mux_mdio_slv1,
+ msm_mux_mdio_slv2,
+ msm_mux_mux_tod_out,
+ msm_mux_pcie0_clk_req_n,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk_req_n,
+ msm_mux_pcie1_wake,
+ msm_mux_pll_test,
+ msm_mux_pon_active_led,
+ msm_mux_pon_mux_sel,
+ msm_mux_pon_rx,
+ msm_mux_pon_rx_los,
+ msm_mux_pon_tx,
+ msm_mux_pon_tx_burst,
+ msm_mux_pon_tx_dis,
+ msm_mux_pon_tx_fault,
+ msm_mux_pon_tx_sd,
+ msm_mux_gpn_rx_los,
+ msm_mux_gpn_tx_burst,
+ msm_mux_gpn_tx_dis,
+ msm_mux_gpn_tx_fault,
+ msm_mux_gpn_tx_sd,
+ msm_mux_pps,
+ msm_mux_pwm_out00,
+ msm_mux_pwm_out01,
+ msm_mux_pwm_out02,
+ msm_mux_pwm_out03,
+ msm_mux_pwm_out10,
+ msm_mux_pwm_out11,
+ msm_mux_pwm_out12,
+ msm_mux_pwm_out20,
+ msm_mux_pwm_out21,
+ msm_mux_pwm_out22,
+ msm_mux_pwm_out30,
+ msm_mux_pwm_out31,
+ msm_mux_pwm_out32,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qrng_rosc0,
+ msm_mux_qrng_rosc1,
+ msm_mux_qrng_rosc2,
+ msm_mux_qspi_data,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs_n,
+ msm_mux_qup_se0_l0,
+ msm_mux_qup_se0_l1,
+ msm_mux_qup_se0_l2,
+ msm_mux_qup_se0_l3,
+ msm_mux_qup_se0_l4,
+ msm_mux_qup_se0_l5,
+ msm_mux_qup_se1_l0,
+ msm_mux_qup_se1_l1,
+ msm_mux_qup_se1_l2,
+ msm_mux_qup_se1_l3,
+ msm_mux_qup_se2_l00,
+ msm_mux_qup_se2_l01,
+ msm_mux_qup_se2_l10,
+ msm_mux_qup_se2_l11,
+ msm_mux_qup_se2_l2,
+ msm_mux_qup_se2_l3,
+ msm_mux_qup_se3_l0,
+ msm_mux_qup_se3_l1,
+ msm_mux_qup_se3_l2,
+ msm_mux_qup_se3_l3,
+ msm_mux_qup_se4_l0,
+ msm_mux_qup_se4_l1,
+ msm_mux_qup_se4_l2,
+ msm_mux_qup_se4_l3,
+ msm_mux_qup_se4_l4,
+ msm_mux_qup_se4_l5,
+ msm_mux_qup_se5_l00,
+ msm_mux_qup_se5_l01,
+ msm_mux_qup_se5_l10,
+ msm_mux_qup_se5_l11,
+ msm_mux_qup_se5_l2,
+ msm_mux_qup_se5_l3,
+ msm_mux_qup_se5_l4,
+ msm_mux_qup_se5_l5,
+ msm_mux_resout,
+ msm_mux_rx_los00,
+ msm_mux_rx_los01,
+ msm_mux_rx_los10,
+ msm_mux_rx_los11,
+ msm_mux_rx_los20,
+ msm_mux_rx_los21,
+ msm_mux_sdc_clk,
+ msm_mux_sdc_cmd,
+ msm_mux_sdc_data,
+ msm_mux_tsens_max,
+ msm_mux__,
+};
+
+static const char *const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
+ "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
+ "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
+ "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
+ "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+ "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char *const atest_char_start_groups[] = {
+ "gpio46",
+};
+
+static const char *const atest_char_status0_groups[] = {
+ "gpio34",
+};
+
+static const char *const atest_char_status1_groups[] = {
+ "gpio35",
+};
+
+static const char *const atest_char_status2_groups[] = {
+ "gpio36",
+};
+
+static const char *const atest_char_status3_groups[] = {
+ "gpio37",
+};
+
+static const char *const atest_tic_en_groups[] = {
+ "gpio42",
+};
+
+static const char *const audio_pri0_groups[] = {
+ "gpio12",
+};
+
+static const char *const audio_pri1_groups[] = {
+ "gpio19",
+};
+
+static const char *const audio_pri2_groups[] = {
+ "gpio8",
+};
+
+static const char *const audio_pri3_groups[] = {
+ "gpio13",
+};
+
+static const char *const audio_pri_d0_groups[] = {
+ "gpio34",
+};
+
+static const char *const audio_pri_d1_groups[] = {
+ "gpio35",
+};
+
+static const char *const audio_pri_fsync_groups[] = {
+ "gpio36",
+};
+
+static const char *const audio_pri_pclk_groups[] = {
+ "gpio37",
+};
+
+static const char *const audio_sec0_groups[] = {
+ "gpio17",
+};
+
+static const char *const audio_sec1_groups[] = {
+ "gpio16",
+};
+
+static const char *const audio_sec2_groups[] = {
+ "gpio49",
+};
+
+static const char *const audio_sec3_groups[] = {
+ "gpio50",
+};
+
+static const char *const audio_sec_d0_groups[] = {
+ "gpio43",
+};
+
+static const char *const audio_sec_d1_groups[] = {
+ "gpio42",
+};
+
+static const char *const audio_sec_fsync_groups[] = {
+ "gpio40",
+};
+
+static const char *const audio_sec_pclk_groups[] = {
+ "gpio41",
+};
+
+static const char *const core_voltage_0_groups[] = {
+ "gpio22",
+};
+
+static const char *const cri_trng0_groups[] = {
+ "gpio6",
+};
+
+static const char *const cri_trng1_groups[] = {
+ "gpio7",
+};
+
+static const char *const cri_trng2_groups[] = {
+ "gpio8",
+};
+
+static const char *const cri_trng3_groups[] = {
+ "gpio9",
+};
+
+static const char *const dbg_out_clk_groups[] = {
+ "gpio23",
+};
+
+static const char *const dg_out_groups[] = {
+ "gpio46",
+};
+
+static const char *const gcc_plltest_bypassnl_groups[] = {
+ "gpio38",
+};
+
+static const char *const gcc_plltest_resetn_groups[] = {
+ "gpio40",
+};
+
+static const char *const gcc_tlmm_groups[] = {
+ "gpio39",
+};
+
+static const char *const Led00_groups[] = {
+ "gpio23",
+};
+
+static const char *const led01_groups[] = {
+ "gpio39",
+};
+
+static const char *const led02_groups[] = {
+ "gpio6",
+};
+
+static const char *const led10_groups[] = {
+ "gpio39",
+};
+
+static const char *const led11_groups[] = {
+ "gpio27",
+};
+
+static const char *const led12_groups[] = {
+ "gpio7",
+};
+
+static const char *const led20_groups[] = {
+ "gpio38",
+};
+
+static const char *const led21_groups[] = {
+ "gpio26",
+};
+
+static const char *const led22_groups[] = {
+ "gpio9",
+};
+
+static const char *const mdc_mst_groups[] = {
+ "gpio26",
+};
+
+static const char *const mdc_slv0_groups[] = {
+ "gpio31",
+};
+
+static const char *const mdc_slv1_groups[] = {
+ "gpio20",
+};
+
+static const char *const mdc_slv2_groups[] = {
+ "gpio47",
+};
+
+static const char *const mdio_mst_groups[] = {
+ "gpio27",
+};
+
+static const char *const mdio_slv0_groups[] = {
+ "gpio33",
+};
+
+static const char *const mdio_slv1_groups[] = {
+ "gpio21",
+};
+
+static const char *const mdio_slv2_groups[] = {
+ "gpio49",
+};
+
+static const char *const mux_tod_out_groups[] = {
+ "gpio19",
+};
+
+static const char *const pcie0_clk_req_n_groups[] = {
+ "gpio31",
+};
+
+static const char *const pcie0_wake_groups[] = {
+ "gpio33",
+};
+
+static const char *const pcie1_clk_req_n_groups[] = {
+ "gpio28",
+};
+
+static const char *const pcie1_wake_groups[] = {
+ "gpio30",
+};
+
+static const char *const pll_test_groups[] = {
+ "gpio18",
+};
+
+static const char *const pon_active_led_groups[] = {
+ "gpio11",
+};
+
+static const char *const pon_mux_sel_groups[] = {
+ "gpio45",
+};
+
+static const char *const pon_rx_groups[] = {
+ "gpio48",
+};
+
+static const char *const pon_rx_los_groups[] = {
+ "gpio10",
+};
+
+static const char *const pon_tx_groups[] = {
+ "gpio15",
+};
+
+static const char *const pon_tx_burst_groups[] = {
+ "gpio14",
+};
+
+static const char *const pon_tx_dis_groups[] = {
+ "gpio12",
+};
+
+static const char *const pon_tx_fault_groups[] = {
+ "gpio17",
+};
+
+static const char *const pon_tx_sd_groups[] = {
+ "gpio16",
+};
+
+static const char *const gpn_rx_los_groups[] = {
+ "gpio47",
+};
+
+static const char *const gpn_tx_burst_groups[] = {
+ "gpio51",
+};
+
+static const char *const gpn_tx_dis_groups[] = {
+ "gpio13",
+};
+
+static const char *const gpn_tx_fault_groups[] = {
+ "gpio49",
+};
+
+static const char *const gpn_tx_sd_groups[] = {
+ "gpio50",
+};
+
+static const char *const pps_groups[] = {
+ "gpio18",
+};
+
+static const char *const pwm_out00_groups[] = {
+ "gpio13",
+};
+
+static const char *const pwm_out01_groups[] = {
+ "gpio9",
+};
+
+static const char *const pwm_out02_groups[] = {
+ "gpio3",
+};
+
+static const char *const pwm_out03_groups[] = {
+ "gpio22",
+};
+
+static const char *const pwm_out10_groups[] = {
+ "gpio12",
+};
+
+static const char *const pwm_out11_groups[] = {
+ "gpio8",
+};
+
+static const char *const pwm_out12_groups[] = {
+ "gpio2",
+};
+
+static const char *const pwm_out20_groups[] = {
+ "gpio11",
+};
+
+static const char *const pwm_out21_groups[] = {
+ "gpio7",
+};
+
+static const char *const pwm_out22_groups[] = {
+ "gpio1",
+};
+
+static const char *const pwm_out30_groups[] = {
+ "gpio10",
+};
+
+static const char *const pwm_out31_groups[] = {
+ "gpio6",
+};
+
+static const char *const pwm_out32_groups[] = {
+ "gpio0",
+};
+
+static const char *const qdss_cti_trig_in_a0_groups[] = {
+ "gpio30",
+};
+
+static const char *const qdss_cti_trig_in_a1_groups[] = {
+ "gpio33",
+};
+
+static const char *const qdss_cti_trig_in_b0_groups[] = {
+ "gpio34",
+};
+
+static const char *const qdss_cti_trig_in_b1_groups[] = {
+ "gpio37",
+};
+
+static const char *const qdss_cti_trig_out_a0_groups[] = {
+ "gpio28",
+};
+
+static const char *const qdss_cti_trig_out_a1_groups[] = {
+ "gpio31",
+};
+
+static const char *const qdss_cti_trig_out_b0_groups[] = {
+ "gpio16",
+};
+
+static const char *const qdss_cti_trig_out_b1_groups[] = {
+ "gpio35",
+};
+
+static const char *const qdss_traceclk_a_groups[] = {
+ "gpio23",
+};
+
+static const char *const qdss_tracectl_a_groups[] = {
+ "gpio26",
+};
+
+static const char *const qdss_tracedata_a_groups[] = {
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21",
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char *const qrng_rosc0_groups[] = {
+ "gpio12",
+};
+
+static const char *const qrng_rosc1_groups[] = {
+ "gpio13",
+};
+
+static const char *const qrng_rosc2_groups[] = {
+ "gpio14",
+};
+
+static const char *const qspi_data_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char *const qspi_clk_groups[] = {
+ "gpio5",
+};
+
+static const char *const qspi_cs_n_groups[] = {
+ "gpio4",
+};
+
+static const char *const qup_se0_l0_groups[] = {
+ "gpio8",
+};
+
+static const char *const qup_se0_l1_groups[] = {
+ "gpio9",
+};
+
+static const char *const qup_se0_l2_groups[] = {
+ "gpio6",
+};
+
+static const char *const qup_se0_l3_groups[] = {
+ "gpio7",
+};
+
+static const char *const qup_se0_l4_groups[] = {
+ "gpio14",
+};
+
+static const char *const qup_se0_l5_groups[] = {
+ "gpio15",
+};
+
+static const char *const qup_se1_l0_groups[] = {
+ "gpio30",
+};
+
+static const char *const qup_se1_l1_groups[] = {
+ "gpio28",
+};
+
+static const char *const qup_se1_l2_groups[] = {
+ "gpio39",
+};
+
+static const char *const qup_se1_l3_groups[] = {
+ "gpio38",
+};
+
+static const char *const qup_se2_l00_groups[] = {
+ "gpio21",
+};
+
+static const char *const qup_se2_l01_groups[] = {
+ "gpio53",
+};
+
+static const char *const qup_se2_l10_groups[] = {
+ "gpio20",
+};
+
+static const char *const qup_se2_l11_groups[] = {
+ "gpio52",
+};
+
+static const char *const qup_se2_l2_groups[] = {
+ "gpio13",
+};
+
+static const char *const qup_se2_l3_groups[] = {
+ "gpio12",
+};
+
+static const char *const qup_se3_l0_groups[] = {
+ "gpio23",
+};
+
+static const char *const qup_se3_l1_groups[] = {
+ "gpio22",
+};
+
+static const char *const qup_se3_l2_groups[] = {
+ "gpio11",
+};
+
+static const char *const qup_se3_l3_groups[] = {
+ "gpio10",
+};
+
+static const char *const qup_se4_l0_groups[] = {
+ "gpio42",
+};
+
+static const char *const qup_se4_l1_groups[] = {
+ "gpio43",
+};
+
+static const char *const qup_se4_l2_groups[] = {
+ "gpio40",
+};
+
+static const char *const qup_se4_l3_groups[] = {
+ "gpio41",
+};
+
+static const char *const qup_se4_l4_groups[] = {
+ "gpio52",
+};
+
+static const char *const qup_se4_l5_groups[] = {
+ "gpio53",
+};
+
+static const char *const qup_se5_l00_groups[] = {
+ "gpio49",
+};
+
+static const char *const qup_se5_l01_groups[] = {
+ "gpio52",
+};
+
+static const char *const qup_se5_l10_groups[] = {
+ "gpio50",
+};
+
+static const char *const qup_se5_l11_groups[] = {
+ "gpio53",
+};
+
+static const char *const qup_se5_l2_groups[] = {
+ "gpio47",
+};
+
+static const char *const qup_se5_l3_groups[] = {
+ "gpio48",
+};
+
+static const char *const qup_se5_l4_groups[] = {
+ "gpio51",
+};
+
+static const char *const qup_se5_l5_groups[] = {
+ "gpio52",
+};
+
+static const char *const resout_groups[] = {
+ "gpio44",
+};
+
+static const char *const rx_los00_groups[] = {
+ "gpio42",
+};
+
+static const char *const rx_los01_groups[] = {
+ "gpio37",
+};
+
+static const char *const rx_los10_groups[] = {
+ "gpio41",
+};
+
+static const char *const rx_los11_groups[] = {
+ "gpio36",
+};
+
+static const char *const rx_los20_groups[] = {
+ "gpio40",
+};
+
+static const char *const rx_los21_groups[] = {
+ "gpio35",
+};
+
+static const char *const sdc_clk_groups[] = {
+ "gpio5",
+};
+
+static const char *const sdc_cmd_groups[] = {
+ "gpio4",
+};
+
+static const char *const sdc_data_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char *const tsens_max_groups[] = {
+ "gpio20",
+};
+
+static const struct pinfunction ipq5210_functions[] = {
+ MSM_PIN_FUNCTION(atest_char_start),
+ MSM_PIN_FUNCTION(atest_char_status0),
+ MSM_PIN_FUNCTION(atest_char_status1),
+ MSM_PIN_FUNCTION(atest_char_status2),
+ MSM_PIN_FUNCTION(atest_char_status3),
+ MSM_PIN_FUNCTION(atest_tic_en),
+ MSM_PIN_FUNCTION(audio_pri0),
+ MSM_PIN_FUNCTION(audio_pri1),
+ MSM_PIN_FUNCTION(audio_pri2),
+ MSM_PIN_FUNCTION(audio_pri3),
+ MSM_PIN_FUNCTION(audio_pri_d0),
+ MSM_PIN_FUNCTION(audio_pri_d1),
+ MSM_PIN_FUNCTION(audio_pri_fsync),
+ MSM_PIN_FUNCTION(audio_pri_pclk),
+ MSM_PIN_FUNCTION(audio_sec0),
+ MSM_PIN_FUNCTION(audio_sec1),
+ MSM_PIN_FUNCTION(audio_sec2),
+ MSM_PIN_FUNCTION(audio_sec3),
+ MSM_PIN_FUNCTION(audio_sec_d0),
+ MSM_PIN_FUNCTION(audio_sec_d1),
+ MSM_PIN_FUNCTION(audio_sec_fsync),
+ MSM_PIN_FUNCTION(audio_sec_pclk),
+ MSM_PIN_FUNCTION(core_voltage_0),
+ MSM_PIN_FUNCTION(cri_trng0),
+ MSM_PIN_FUNCTION(cri_trng1),
+ MSM_PIN_FUNCTION(cri_trng2),
+ MSM_PIN_FUNCTION(cri_trng3),
+ MSM_PIN_FUNCTION(dbg_out_clk),
+ MSM_PIN_FUNCTION(dg_out),
+ MSM_PIN_FUNCTION(gcc_plltest_bypassnl),
+ MSM_PIN_FUNCTION(gcc_plltest_resetn),
+ MSM_PIN_FUNCTION(gcc_tlmm),
+ MSM_GPIO_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(Led00),
+ MSM_PIN_FUNCTION(led01),
+ MSM_PIN_FUNCTION(led02),
+ MSM_PIN_FUNCTION(led10),
+ MSM_PIN_FUNCTION(led11),
+ MSM_PIN_FUNCTION(led12),
+ MSM_PIN_FUNCTION(led20),
+ MSM_PIN_FUNCTION(led21),
+ MSM_PIN_FUNCTION(led22),
+ MSM_PIN_FUNCTION(mdc_mst),
+ MSM_PIN_FUNCTION(mdc_slv0),
+ MSM_PIN_FUNCTION(mdc_slv1),
+ MSM_PIN_FUNCTION(mdc_slv2),
+ MSM_PIN_FUNCTION(mdio_mst),
+ MSM_PIN_FUNCTION(mdio_slv0),
+ MSM_PIN_FUNCTION(mdio_slv1),
+ MSM_PIN_FUNCTION(mdio_slv2),
+ MSM_PIN_FUNCTION(mux_tod_out),
+ MSM_PIN_FUNCTION(pcie0_clk_req_n),
+ MSM_PIN_FUNCTION(pcie0_wake),
+ MSM_PIN_FUNCTION(pcie1_clk_req_n),
+ MSM_PIN_FUNCTION(pcie1_wake),
+ MSM_PIN_FUNCTION(pll_test),
+ MSM_PIN_FUNCTION(pon_active_led),
+ MSM_PIN_FUNCTION(pon_mux_sel),
+ MSM_PIN_FUNCTION(pon_rx),
+ MSM_PIN_FUNCTION(pon_rx_los),
+ MSM_PIN_FUNCTION(pon_tx),
+ MSM_PIN_FUNCTION(pon_tx_burst),
+ MSM_PIN_FUNCTION(pon_tx_dis),
+ MSM_PIN_FUNCTION(pon_tx_fault),
+ MSM_PIN_FUNCTION(pon_tx_sd),
+ MSM_PIN_FUNCTION(gpn_rx_los),
+ MSM_PIN_FUNCTION(gpn_tx_burst),
+ MSM_PIN_FUNCTION(gpn_tx_dis),
+ MSM_PIN_FUNCTION(gpn_tx_fault),
+ MSM_PIN_FUNCTION(gpn_tx_sd),
+ MSM_PIN_FUNCTION(pps),
+ MSM_PIN_FUNCTION(pwm_out00),
+ MSM_PIN_FUNCTION(pwm_out01),
+ MSM_PIN_FUNCTION(pwm_out02),
+ MSM_PIN_FUNCTION(pwm_out03),
+ MSM_PIN_FUNCTION(pwm_out10),
+ MSM_PIN_FUNCTION(pwm_out11),
+ MSM_PIN_FUNCTION(pwm_out12),
+ MSM_PIN_FUNCTION(pwm_out20),
+ MSM_PIN_FUNCTION(pwm_out21),
+ MSM_PIN_FUNCTION(pwm_out22),
+ MSM_PIN_FUNCTION(pwm_out30),
+ MSM_PIN_FUNCTION(pwm_out31),
+ MSM_PIN_FUNCTION(pwm_out32),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
+ MSM_PIN_FUNCTION(qdss_traceclk_a),
+ MSM_PIN_FUNCTION(qdss_tracectl_a),
+ MSM_PIN_FUNCTION(qdss_tracedata_a),
+ MSM_PIN_FUNCTION(qrng_rosc0),
+ MSM_PIN_FUNCTION(qrng_rosc1),
+ MSM_PIN_FUNCTION(qrng_rosc2),
+ MSM_PIN_FUNCTION(qspi_data),
+ MSM_PIN_FUNCTION(qspi_clk),
+ MSM_PIN_FUNCTION(qspi_cs_n),
+ MSM_PIN_FUNCTION(qup_se0_l0),
+ MSM_PIN_FUNCTION(qup_se0_l1),
+ MSM_PIN_FUNCTION(qup_se0_l2),
+ MSM_PIN_FUNCTION(qup_se0_l3),
+ MSM_PIN_FUNCTION(qup_se0_l4),
+ MSM_PIN_FUNCTION(qup_se0_l5),
+ MSM_PIN_FUNCTION(qup_se1_l0),
+ MSM_PIN_FUNCTION(qup_se1_l1),
+ MSM_PIN_FUNCTION(qup_se1_l2),
+ MSM_PIN_FUNCTION(qup_se1_l3),
+ MSM_PIN_FUNCTION(qup_se2_l00),
+ MSM_PIN_FUNCTION(qup_se2_l01),
+ MSM_PIN_FUNCTION(qup_se2_l10),
+ MSM_PIN_FUNCTION(qup_se2_l11),
+ MSM_PIN_FUNCTION(qup_se2_l2),
+ MSM_PIN_FUNCTION(qup_se2_l3),
+ MSM_PIN_FUNCTION(qup_se3_l0),
+ MSM_PIN_FUNCTION(qup_se3_l1),
+ MSM_PIN_FUNCTION(qup_se3_l2),
+ MSM_PIN_FUNCTION(qup_se3_l3),
+ MSM_PIN_FUNCTION(qup_se4_l0),
+ MSM_PIN_FUNCTION(qup_se4_l1),
+ MSM_PIN_FUNCTION(qup_se4_l2),
+ MSM_PIN_FUNCTION(qup_se4_l3),
+ MSM_PIN_FUNCTION(qup_se4_l4),
+ MSM_PIN_FUNCTION(qup_se4_l5),
+ MSM_PIN_FUNCTION(qup_se5_l00),
+ MSM_PIN_FUNCTION(qup_se5_l01),
+ MSM_PIN_FUNCTION(qup_se5_l10),
+ MSM_PIN_FUNCTION(qup_se5_l11),
+ MSM_PIN_FUNCTION(qup_se5_l2),
+ MSM_PIN_FUNCTION(qup_se5_l3),
+ MSM_PIN_FUNCTION(qup_se5_l4),
+ MSM_PIN_FUNCTION(qup_se5_l5),
+ MSM_PIN_FUNCTION(resout),
+ MSM_PIN_FUNCTION(rx_los00),
+ MSM_PIN_FUNCTION(rx_los01),
+ MSM_PIN_FUNCTION(rx_los10),
+ MSM_PIN_FUNCTION(rx_los11),
+ MSM_PIN_FUNCTION(rx_los20),
+ MSM_PIN_FUNCTION(rx_los21),
+ MSM_PIN_FUNCTION(sdc_clk),
+ MSM_PIN_FUNCTION(sdc_cmd),
+ MSM_PIN_FUNCTION(sdc_data),
+ MSM_PIN_FUNCTION(tsens_max),
+};
+
+static const struct msm_pingroup ipq5210_groups[] = {
+ [0] = PINGROUP(0, sdc_data, qspi_data, pwm_out32, _, _, _, _, _, _),
+ [1] = PINGROUP(1, sdc_data, qspi_data, pwm_out22, _, _, _, _, _, _),
+ [2] = PINGROUP(2, sdc_data, qspi_data, pwm_out12, _, _, _, _, _, _),
+ [3] = PINGROUP(3, sdc_data, qspi_data, pwm_out02, _, _, _, _, _, _),
+ [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),
+ [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
+ [6] = PINGROUP(6, qup_se0_l2, led02, pwm_out31, _, cri_trng0, qdss_tracedata_a, _, _, _),
+ [7] = PINGROUP(7, qup_se0_l3, led12, pwm_out21, _, cri_trng1, qdss_tracedata_a, _, _, _),
+ [8] = PINGROUP(8, qup_se0_l0, pwm_out11, audio_pri2, audio_pri2, _, cri_trng2, qdss_tracedata_a, _, _),
+ [9] = PINGROUP(9, qup_se0_l1, led22, pwm_out01, _, cri_trng3, qdss_tracedata_a, _, _, _),
+ [10] = PINGROUP(10, pon_rx_los, qup_se3_l3, pwm_out30, _, _, qdss_tracedata_a, _, _, _),
+ [11] = PINGROUP(11, pon_active_led, qup_se3_l2, pwm_out20, _, _, qdss_tracedata_a, _, _, _),
+ [12] = PINGROUP(12, pon_tx_dis, qup_se2_l3, pwm_out10, audio_pri0, audio_pri0, _, qrng_rosc0, qdss_tracedata_a, _),
+ [13] = PINGROUP(13, gpn_tx_dis, qup_se2_l2, pwm_out00, audio_pri3, audio_pri3, _, qrng_rosc1, qdss_tracedata_a, _),
+ [14] = PINGROUP(14, pon_tx_burst, qup_se0_l4, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _),
+ [15] = PINGROUP(15, pon_tx, qup_se0_l5, _, qdss_tracedata_a, _, _, _, _, _),
+ [16] = PINGROUP(16, pon_tx_sd, audio_sec1, audio_sec1, qdss_cti_trig_out_b0, _, _, _, _, _),
+ [17] = PINGROUP(17, pon_tx_fault, audio_sec0, audio_sec0, _, _, _, _, _, _),
+ [18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _),
+ [19] = PINGROUP(19, mux_tod_out, audio_pri1, audio_pri1, _, _, _, _, _, _),
+ [20] = PINGROUP(20, qup_se2_l10, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _),
+ [21] = PINGROUP(21, qup_se2_l00, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _),
+ [22] = PINGROUP(22, core_voltage_0, qup_se3_l1, pwm_out03, _, _, _, _, _, _),
+ [23] = PINGROUP(23, Led00, qup_se3_l0, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _),
+ [24] = PINGROUP(24, _, _, _, _, _, _, _, _, _),
+ [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
+ [26] = PINGROUP(26, mdc_mst, led21, _, qdss_tracectl_a, _, _, _, _, _),
+ [27] = PINGROUP(27, mdio_mst, led11, _, _, _, _, _, _, _),
+ [28] = PINGROUP(28, pcie1_clk_req_n, qup_se1_l1, _, _, qdss_cti_trig_out_a0, _, _, _, _),
+ [29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
+ [30] = PINGROUP(30, pcie1_wake, qup_se1_l0, _, _, qdss_cti_trig_in_a0, _, _, _, _),
+ [31] = PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _),
+ [32] = PINGROUP(32, _, _, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _),
+ [34] = PINGROUP(34, audio_pri_d0, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _),
+ [35] = PINGROUP(35, audio_pri_d1, rx_los21, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _),
+ [36] = PINGROUP(36, audio_pri_fsync, _, rx_los11, atest_char_status2, _, _, _, _, _),
+ [37] = PINGROUP(37, audio_pri_pclk, rx_los01, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _),
+ [38] = PINGROUP(38, qup_se1_l3, led20, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _),
+ [39] = PINGROUP(39, qup_se1_l2, led10, led01, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
+ [40] = PINGROUP(40, qup_se4_l2, rx_los20, audio_sec_fsync, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _),
+ [41] = PINGROUP(41, qup_se4_l3, rx_los10, audio_sec_pclk, qdss_tracedata_a, _, _, _, _, _),
+ [42] = PINGROUP(42, qup_se4_l0, rx_los00, audio_sec_d1, atest_tic_en, _, _, _, _, _),
+ [43] = PINGROUP(43, qup_se4_l1, audio_sec_d0, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, resout, _, _, _, _, _, _, _, _),
+ [45] = PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _),
+ [46] = PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5_l2, _, _, _, _, _, _),
+ [48] = PINGROUP(48, pon_rx, qup_se5_l3, _, _, _, _, _, _, _),
+ [49] = PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5_l00, audio_sec2, audio_sec2, _, _, _, _),
+ [50] = PINGROUP(50, gpn_tx_sd, qup_se5_l10, audio_sec3, audio_sec3, _, _, _, _, _),
+ [51] = PINGROUP(51, gpn_tx_burst, qup_se5_l4, _, _, _, _, _, _, _),
+ [52] = PINGROUP(52, qup_se2_l11, qup_se5_l5, qup_se4_l4, qup_se5_l01, _, _, _, _, _),
+ [53] = PINGROUP(53, qup_se2_l01, qup_se4_l5, qup_se5_l11, _, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq5210_tlmm = {
+ .pins = ipq5210_pins,
+ .npins = ARRAY_SIZE(ipq5210_pins),
+ .functions = ipq5210_functions,
+ .nfunctions = ARRAY_SIZE(ipq5210_functions),
+ .groups = ipq5210_groups,
+ .ngroups = ARRAY_SIZE(ipq5210_groups),
+ .ngpios = 54,
+};
+
+static const struct of_device_id ipq5210_tlmm_of_match[] = {
+ { .compatible = "qcom,ipq5210-tlmm", },
+ { },
+};
+
+static int ipq5210_tlmm_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq5210_tlmm);
+}
+
+static struct platform_driver ipq5210_tlmm_driver = {
+ .driver = {
+ .name = "ipq5210-tlmm",
+ .of_match_table = ipq5210_tlmm_of_match,
+ },
+ .probe = ipq5210_tlmm_probe,
+};
+
+static int __init ipq5210_tlmm_init(void)
+{
+ return platform_driver_register(&ipq5210_tlmm_driver);
+}
+arch_initcall(ipq5210_tlmm_init);
+
+static void __exit ipq5210_tlmm_exit(void)
+{
+ platform_driver_unregister(&ipq5210_tlmm_driver);
+}
+module_exit(ipq5210_tlmm_exit);
+
+MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (3 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:20 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible Kathiravan Thirumoorthy
` (5 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Document the new ipq5210 SoC/board device tree bindings.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index d95acd4a424d368a481aa49d66449f784cf81986..9bf291511bc8910f0118e2e804c07c02770d5fd1 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -309,6 +309,11 @@ properties:
- tplink,archer-ax55-v1
- const: qcom,ipq5018
+ - items:
+ - enum:
+ - qcom,ipq5210-rdp504
+ - const: qcom,ipq5210
+
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (4 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-16 15:15 ` Ulf Hansson
2026-03-11 9:45 ` [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM Kathiravan Thirumoorthy
` (4 subsequent siblings)
10 siblings, 2 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
The IPQ5210 supports eMMC with an SDHCI controller. Add the appropriate
compatible to the documentation.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 938be8228d668c87f0be95c63d4d951ebbadd4e4..fd1d5b04e7556903daffe86e455fde11be0dbd9f 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -38,6 +38,7 @@ properties:
- items:
- enum:
- qcom,ipq5018-sdhci
+ - qcom,ipq5210-sdhci
- qcom,ipq5332-sdhci
- qcom,ipq5424-sdhci
- qcom,ipq6018-sdhci
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (5 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Kathiravan Thirumoorthy
` (3 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Document the scm compatible for ipq5210 SoC.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index d66459f1d84e4d99c7f72415d08bfdaf1d701948..6d9b71a9b9b3fefd1951b963f34942243aa48ccb 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,scm-glymur
- qcom,scm-ipq4019
- qcom,scm-ipq5018
+ - qcom,scm-ipq5210
- qcom,scm-ipq5332
- qcom,scm-ipq5424
- qcom,scm-ipq6018
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (6 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 12:48 ` Konrad Dybcio
2026-03-11 9:45 ` [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs Kathiravan Thirumoorthy
` (2 subsequent siblings)
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Add initial device tree support for the Qualcomm IPQ5210 SoC and
rdp504 board.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++++++
3 files changed, 398 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37aa441444c2b13 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
new file mode 100644
index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f0a1e80848c8de
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "ipq5210.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
+ compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ soc@0 {
+ qupv3: geniqup@1ac0000 {
+ status = "okay";
+
+ uart1: serial@1a84000 {
+ pinctrl-0 = <&qup_uart1_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+ };
+};
+
+&sdhc {
+ max-frequency = <192000000>;
+ bus-width = <4>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ pinctrl-0 = <&sdhc_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ qup_uart1_default_state: qup-uart1-default-state {
+ tx-pins {
+ pins = "gpio39";
+ function = "qup_se1_l2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ rx-pins {
+ pins = "gpio38";
+ function = "qup_se1_l3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+ };
+
+ sdhc_default_state: sdhc-default-state {
+ clk-pins {
+ pins = "gpio5";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio4";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&xo {
+ clock-frequency = <24000000>;
+};
+
diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..b959162737c87d8c44fd18cd7e954f85f797085a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo: xo {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <0x2>;
+ cache-unified;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scm {
+ compatible = "qcom,scm-ipq5210", "qcom,scm";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bootloader@87800000 {
+ reg = <0x0 0x87800000 0x0 0x400000>;
+ no-map;
+ };
+
+ smem@87c00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x87c00000 0x0 0x40000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ tfa@87d00000 {
+ reg = <0x0 0x87d00000 0x0 0x80000>;
+ no-map;
+ };
+
+ optee@87d80000 {
+ reg = <0x0 0x87d80000 0x0 0x280000>;
+ no-map;
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5210-tlmm";
+ reg = <0x0 0x01000000 0x0 0x300000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 54>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,ipq5210-gcc";
+ reg = <0x0 0x01800000 0x0 0x40000>;
+ clocks = <&xo>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01905000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ qupv3: geniqup@1ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x01ac0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
+ <&gcc GCC_QUPV3_AHB_SLV_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ status = "disabled";
+
+ uart1: serial@1a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ sdhc: mmc@7804000 {
+ compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>;
+ reg-names = "hc",
+ "cqhci";
+
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>;
+ clock-names = "iface",
+ "core",
+ "xo";
+ non-removable;
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0 0xb000000 0x0 0x1000>, /* GICD */
+ <0x0 0xb002000 0x0 0x1000>, /* GICC */
+ <0x0 0xb001000 0x0 0x1000>, /* GICH */
+ <0x0 0xb004000 0x0 0x1000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0x0b00c000 0 0x3000>;
+
+ v2m0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x0 0x0 0x0 0xffd>;
+ msi-controller;
+ };
+
+ v2m1: v2m@1000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x0 0x00001000 0x0 0xffd>;
+ msi-controller;
+ };
+
+ v2m2: v2m@2000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x0 0x00002000 0x0 0xffd>;
+ msi-controller;
+ };
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0xb120000 0x0 0x1000>;
+ ranges = <0 0 0 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ frame@b121000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b128000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (7 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Kathiravan Thirumoorthy
@ 2026-03-11 9:45 ` Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-11 13:01 ` [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Linus Walleij
2026-03-13 13:25 ` Krzysztof Kozlowski
10 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-11 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc, Kathiravan Thirumoorthy
Enable GCC, Pinctrl for Qualcomm's IPQ5210 SoC which is required to boot
ipq5210-rdp504 board to a console shell.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4ed70ab7ee854038fa7a756d8b650a609258bdb3..59c748efc1ca8d6eb7dca19011d2a31d926a0d43 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -649,6 +649,7 @@ CONFIG_PINCTRL_IMX_SCMI=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_GLYMUR=y
CONFIG_PINCTRL_IPQ5018=y
+CONFIG_PINCTRL_IPQ5210=y
CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ5424=y
CONFIG_PINCTRL_IPQ8074=y
@@ -1476,6 +1477,7 @@ CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_CMN_PLL=m
CONFIG_IPQ_GCC_5018=y
+CONFIG_IPQ_GCC_5210=y
CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_5424=y
CONFIG_IPQ_GCC_6018=y
--
2.34.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (8 preceding siblings ...)
2026-03-11 9:45 ` [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs Kathiravan Thirumoorthy
@ 2026-03-11 13:01 ` Linus Walleij
2026-03-13 6:55 ` Kathiravan Thirumoorthy
2026-03-13 13:25 ` Krzysztof Kozlowski
10 siblings, 1 reply; 34+ messages in thread
From: Linus Walleij @ 2026-03-11 13:01 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Konrad Dybcio,
Ulf Hansson, Robert Marko, Guru Das Srinagesh, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-gpio, linux-mmc
Hi Kathiravan,
thanks for your patches!
On Wed, Mar 11, 2026 at 10:45 AM Kathiravan Thirumoorthy
<kathiravan.thirumoorthy@oss.qualcomm.com> wrote:
> dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
> pinctrl: qcom: Introduce IPQ5210 TLMM driver
Can you send these two separately?
It seems I can just apply them to the pinctrl tree after review,
no dependency on the other patches, right?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-11 9:45 ` [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Kathiravan Thirumoorthy
@ 2026-03-11 14:45 ` Dmitry Baryshkov
2026-03-13 12:54 ` Konrad Dybcio
1 sibling, 0 replies; 34+ messages in thread
From: Dmitry Baryshkov @ 2026-03-11 14:45 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:46PM +0530, Kathiravan Thirumoorthy wrote:
> Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
> so add a driver for it.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> drivers/pinctrl/qcom/Kconfig.msm | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq5210.c | 1156 ++++++++++++++++++++++++++++++++
> 3 files changed, 1165 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC
2026-03-11 9:45 ` [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC Kathiravan Thirumoorthy
@ 2026-03-11 14:50 ` Dmitry Baryshkov
2026-03-13 8:42 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 34+ messages in thread
From: Dmitry Baryshkov @ 2026-03-11 14:50 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:44PM +0530, Kathiravan Thirumoorthy wrote:
> Add support for the global clock controller found on IPQ5210 SoC.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> drivers/clk/qcom/Kconfig | 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq5210.c | 2641 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 2650 insertions(+)
>
> +
> +static struct clk_alpha_pll gpll4_main = {
> + .offset = 0x22000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(2),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll4_main",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + .flags = CLK_IS_CRITICAL,
comment, why?
> + },
> + },
> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210
2026-03-11 13:01 ` [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Linus Walleij
@ 2026-03-13 6:55 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-13 6:55 UTC (permalink / raw)
To: Linus Walleij
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Konrad Dybcio,
Ulf Hansson, Robert Marko, Guru Das Srinagesh, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-gpio, linux-mmc
On 3/11/2026 6:31 PM, Linus Walleij wrote:
> Hi Kathiravan,
>
> thanks for your patches!
>
> On Wed, Mar 11, 2026 at 10:45 AM Kathiravan Thirumoorthy
> <kathiravan.thirumoorthy@oss.qualcomm.com> wrote:
>
>> dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
>> pinctrl: qcom: Introduce IPQ5210 TLMM driver
> Can you send these two separately?
>
> It seems I can just apply them to the pinctrl tree after review,
> no dependency on the other patches, right?
Thanks, Linus. Dmitry has reviewed the driver. Should I wait for the DT
maintainers to review the binding, and once it is reviewed, send it
separately, or would you prefer that I send it now?
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC
2026-03-11 14:50 ` Dmitry Baryshkov
@ 2026-03-13 8:42 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-13 8:42 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/11/2026 8:20 PM, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 03:15:44PM +0530, Kathiravan Thirumoorthy wrote:
>> Add support for the global clock controller found on IPQ5210 SoC.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> drivers/clk/qcom/Kconfig | 8 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-ipq5210.c | 2641 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 2650 insertions(+)
>>
>> +
>> +static struct clk_alpha_pll gpll4_main = {
>> + .offset = 0x22000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
>> + .clkr = {
>> + .enable_reg = 0xb000,
>> + .enable_mask = BIT(2),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll4_main",
>> + .parent_data = &gcc_parent_data_xo,
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + .flags = CLK_IS_CRITICAL,
> comment, why?
Sure, let me add something like below in the next spin. Will that be okay?
/*
* There are no consumers for this source in kernel yet,
* (will be added soon), so the clock framework
* disables this source. But some of the clocks
* initialized by boot loaders uses this source. So we
* need to keep this clock ON. Add the
* CLK_IS_CRITICAL flag so the clock will not be
* disabled. Once the consumer in kernel is added, we
* can get rid of this flag.
*/
Thanks,
Kathiravan T.
>
>> + },
>> + },
>> +};
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
2026-03-11 9:45 ` [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Kathiravan Thirumoorthy
@ 2026-03-13 12:48 ` Konrad Dybcio
2026-03-16 9:03 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 34+ messages in thread
From: Konrad Dybcio @ 2026-03-13 12:48 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Linus Walleij, Konrad Dybcio, Ulf Hansson,
Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
> Add initial device tree support for the Qualcomm IPQ5210 SoC and
> rdp504 board.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++
> arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++++++
> 3 files changed, 398 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37aa441444c2b13 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f0a1e80848c8de
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5210.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
> + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
> +
> + aliases {
> + serial0 = &uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc@0 {
> + qupv3: geniqup@1ac0000 {
> + status = "okay";
> +
> + uart1: serial@1a84000 {
Please define this in the SoC DTSI and enable it via a &uart1 {} reference
from the board DT
[...]
> + xo: xo {
"xo_board" is the convention in other DTs
[...]
> + L2_0: l2-cache {
labels must apparently be lowercase nowadays
> + compatible = "cache";
> + cache-level = <0x2>;
= <2>
> + cache-unified;
> + };
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + scm {
> + compatible = "qcom,scm-ipq5210", "qcom,scm";
> + };
OP-TEE *and* SCM? What does the former do?
[...]
> + soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
should dma-ranges also be 36-bit?
[...]
> + qupv3: geniqup@1ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x0 0x01ac0000 0x0 0x2000>;
> + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
> + <&gcc GCC_QUPV3_AHB_SLV_CLK>;
> + clock-names = "m-ahb", "s-ahb";
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + status = "disabled";
I see there's only a single QUP wrapper - therefore I'm going to assume
there will never be a SoC where this needs to be disabled
[...]
> +
> + uart1: serial@1a84000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x0 0x01a84000 0x0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
Please uniformly keep a \n before status, file-wide
Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-11 9:45 ` [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Kathiravan Thirumoorthy
2026-03-11 14:45 ` Dmitry Baryshkov
@ 2026-03-13 12:54 ` Konrad Dybcio
2026-03-16 8:58 ` Kathiravan Thirumoorthy
1 sibling, 1 reply; 34+ messages in thread
From: Konrad Dybcio @ 2026-03-13 12:54 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Linus Walleij, Konrad Dybcio, Ulf Hansson,
Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
> Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
> so add a driver for it.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
[...]
> +static const char *const Led00_groups[] = {
odd uppercase
> + "gpio23",
> +};
> +
> +static const char *const led01_groups[] = {
> + "gpio39",
> +};
> +
> +static const char *const led02_groups[] = {
> + "gpio6",
> +};
What do these 'ledN[012]' functions represent? Are they muxes for
getting activity/status signals for eth/wlan ports?
Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM
2026-03-11 9:45 ` [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM Kathiravan Thirumoorthy
@ 2026-03-13 13:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:19 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:49PM +0530, Kathiravan Thirumoorthy wrote:
> Document the scm compatible for ipq5210 SoC.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs
2026-03-11 9:45 ` [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs Kathiravan Thirumoorthy
@ 2026-03-13 13:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:19 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:51PM +0530, Kathiravan Thirumoorthy wrote:
> Enable GCC, Pinctrl for Qualcomm's IPQ5210 SoC which is required to boot
> ipq5210-rdp504 board to a console shell.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible
2026-03-11 9:45 ` [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible Kathiravan Thirumoorthy
@ 2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-16 15:15 ` Ulf Hansson
1 sibling, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:19 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:48PM +0530, Kathiravan Thirumoorthy wrote:
> The IPQ5210 supports eMMC with an SDHCI controller. Add the appropriate
> compatible to the documentation.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards
2026-03-11 9:45 ` [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards Kathiravan Thirumoorthy
@ 2026-03-13 13:20 ` Krzysztof Kozlowski
0 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:20 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:47PM +0530, Kathiravan Thirumoorthy wrote:
> Document the new ipq5210 SoC/board device tree bindings.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC
2026-03-11 9:45 ` [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC Kathiravan Thirumoorthy
@ 2026-03-13 13:22 ` Krzysztof Kozlowski
2026-03-16 7:16 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:22 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:43PM +0530, Kathiravan Thirumoorthy wrote:
> Add binding for the Qualcomm IPQ5210 Global Clock Controller.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,ipq5210-gcc.yaml | 62 ++++++++++
> include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 ++++++++++++++++++++
> include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++++++
> 3 files changed, 315 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..aeb5d9a3f8322d5d36d2fd19a1d23b275efc34b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on IPQ5210
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> +
> +description: |
> + Qualcomm global clock control module provides the clocks, resets and power
> + domains on IPQ5210
> +
> + See also::
Just a single ':'
> + include/dt-bindings/clock/qcom,ipq5210-gcc.h
> + include/dt-bindings/reset/qcom,ipq5210-gcc.h
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
2026-03-11 9:45 ` [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Kathiravan Thirumoorthy
@ 2026-03-13 13:24 ` Krzysztof Kozlowski
2026-03-16 7:18 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:24 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:45PM +0530, Kathiravan Thirumoorthy wrote:
> Add device tree bindings for IPQ5210 TLMM block.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> .../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++++++
> 1 file changed, 141 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b615c67e642152c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ5210 TLMM pin controller
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> +
> +description: |
Drop |
Please do not combine completely independent series, targetting
different subsystems, into one patchset. It does not bring benefits but
only make everything trickier for maintainers which need to figure out
dependencies and cherry pick instead of applying entire series.
We raised this multiple times and it IS documented in your guideline, so
READ the internal docs.
> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
> +
> +allOf:
> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
...
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq5210-tlmm";
> + reg = <0x01000000 0x300000>;
> + gpio-controller;
> + #gpio-cells = <0x2>;
> + gpio-ranges = <&tlmm 0 0 54>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <0x2>;
> +
> + qup-uart1-default-state {
> + tx-pins {
> + pins = "gpio39";
> + function = "qup_se1_l2";
> + drive-strength = <6>;
> + bias-pull-down;
> + };
> +
> + rx-pins {
> + pins = "gpio38";
> + function = "qup_se1_l3";
> + drive-strength = <6>;
> + bias-pull-down;
> + };
> + };
> +
Drop blank line
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
` (9 preceding siblings ...)
2026-03-11 13:01 ` [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Linus Walleij
@ 2026-03-13 13:25 ` Krzysztof Kozlowski
2026-03-16 7:27 ` Kathiravan Thirumoorthy
10 siblings, 1 reply; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-13 13:25 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On Wed, Mar 11, 2026 at 03:15:42PM +0530, Kathiravan Thirumoorthy wrote:
> The IPQ5210 is Qualcomm's SoC for Routers, Gateways and Access Points. This
> series adds minimal board boot support for ipq5210-rdp504 board.
You combined around four or five independent subsystems. Where are
dependencies and merging conflicts/strategy explained?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC
2026-03-13 13:22 ` Krzysztof Kozlowski
@ 2026-03-16 7:16 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 7:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/13/2026 6:52 PM, Krzysztof Kozlowski wrote:
> On Wed, Mar 11, 2026 at 03:15:43PM +0530, Kathiravan Thirumoorthy wrote:
>> Add binding for the Qualcomm IPQ5210 Global Clock Controller.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> .../bindings/clock/qcom,ipq5210-gcc.yaml | 62 ++++++++++
>> include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 ++++++++++++++++++++
>> include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++++++
>> 3 files changed, 315 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..aeb5d9a3f8322d5d36d2fd19a1d23b275efc34b3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
>> @@ -0,0 +1,62 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller on IPQ5210
>> +
>> +maintainers:
>> + - Bjorn Andersson <andersson@kernel.org>
>> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> +
>> +description: |
>> + Qualcomm global clock control module provides the clocks, resets and power
>> + domains on IPQ5210
>> +
>> + See also::
> Just a single ':'
Ack.
>
>> + include/dt-bindings/clock/qcom,ipq5210-gcc.h
>> + include/dt-bindings/reset/qcom,ipq5210-gcc.h
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Thanks!
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
2026-03-13 13:24 ` Krzysztof Kozlowski
@ 2026-03-16 7:18 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 7:18 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/13/2026 6:54 PM, Krzysztof Kozlowski wrote:
> On Wed, Mar 11, 2026 at 03:15:45PM +0530, Kathiravan Thirumoorthy wrote:
>> Add device tree bindings for IPQ5210 TLMM block.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> .../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++++++
>> 1 file changed, 141 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b615c67e642152c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
>> @@ -0,0 +1,141 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm IPQ5210 TLMM pin controller
>> +
>> +maintainers:
>> + - Bjorn Andersson <andersson@kernel.org>
>> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> +
>> +description: |
> Drop |
Ack.
>
> Please do not combine completely independent series, targetting
> different subsystems, into one patchset. It does not bring benefits but
> only make everything trickier for maintainers which need to figure out
> dependencies and cherry pick instead of applying entire series.
>
> We raised this multiple times and it IS documented in your guideline, so
> READ the internal docs.
Ack.
>
>> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
>> +
>> +allOf:
>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>> +
> ...
>
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + tlmm: pinctrl@1000000 {
>> + compatible = "qcom,ipq5210-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + gpio-controller;
>> + #gpio-cells = <0x2>;
>> + gpio-ranges = <&tlmm 0 0 54>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <0x2>;
>> +
>> + qup-uart1-default-state {
>> + tx-pins {
>> + pins = "gpio39";
>> + function = "qup_se1_l2";
>> + drive-strength = <6>;
>> + bias-pull-down;
>> + };
>> +
>> + rx-pins {
>> + pins = "gpio38";
>> + function = "qup_se1_l3";
>> + drive-strength = <6>;
>> + bias-pull-down;
>> + };
>> + };
>> +
> Drop blank line
Ack.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Thanks!
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210
2026-03-13 13:25 ` Krzysztof Kozlowski
@ 2026-03-16 7:27 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 7:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Ulf Hansson, Robert Marko, Guru Das Srinagesh,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/13/2026 6:55 PM, Krzysztof Kozlowski wrote:
> On Wed, Mar 11, 2026 at 03:15:42PM +0530, Kathiravan Thirumoorthy wrote:
>> The IPQ5210 is Qualcomm's SoC for Routers, Gateways and Access Points. This
>> series adds minimal board boot support for ipq5210-rdp504 board.
> You combined around four or five independent subsystems. Where are
> dependencies and merging conflicts/strategy explained?
Sorry for the inconvenience. I will split up the patches per subsystems
in V2.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-13 12:54 ` Konrad Dybcio
@ 2026-03-16 8:58 ` Kathiravan Thirumoorthy
2026-03-16 9:46 ` Konrad Dybcio
0 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 8:58 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Linus Walleij, Konrad Dybcio, Ulf Hansson, Robert Marko,
Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/13/2026 6:24 PM, Konrad Dybcio wrote:
> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
>> Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
>> so add a driver for it.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
> [...]
>
>> +static const char *const Led00_groups[] = {
> odd uppercase
Yeah, in HW document also only this name has the uppercase. So I just
left it to align with the HW document. Do you prefer to change it to
lower case to maintain consistency?
>
>> + "gpio23",
>> +};
>> +
>> +static const char *const led01_groups[] = {
>> + "gpio39",
>> +};
>> +
>> +static const char *const led02_groups[] = {
>> + "gpio6",
>> +};
> What do these 'ledN[012]' functions represent? Are they muxes for
> getting activity/status signals for eth/wlan ports?
Yes, that's right. These LED functions used for the eth/wlan status.
>
> Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
2026-03-13 12:48 ` Konrad Dybcio
@ 2026-03-16 9:03 ` Kathiravan Thirumoorthy
2026-03-16 9:34 ` Konrad Dybcio
0 siblings, 1 reply; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 9:03 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Linus Walleij, Konrad Dybcio, Ulf Hansson, Robert Marko,
Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/13/2026 6:18 PM, Konrad Dybcio wrote:
> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
>> Add initial device tree support for the Qualcomm IPQ5210 SoC and
>> rdp504 board.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++
>> arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++++++
>> 3 files changed, 398 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37aa441444c2b13 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
>> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f0a1e80848c8de
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
>> @@ -0,0 +1,93 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq5210.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
>> + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
>> +
>> + aliases {
>> + serial0 = &uart1;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc@0 {
>> + qupv3: geniqup@1ac0000 {
>> + status = "okay";
>> +
>> + uart1: serial@1a84000 {
> Please define this in the SoC DTSI and enable it via a &uart1 {} reference
> from the board DT
Ack.
>
> [...]
>
>> + xo: xo {
> "xo_board" is the convention in other DTs
Ack.
>
> [...]
>
>> + L2_0: l2-cache {
> labels must apparently be lowercase nowadays
Ack.
>
>> + compatible = "cache";
>> + cache-level = <0x2>;
> = <2>
Ack.
>
>
>> + cache-unified;
>> + };
>> + };
>> +
>> + firmware {
>> + optee {
>> + compatible = "linaro,optee-tz";
>> + method = "smc";
>> + };
>> +
>> + scm {
>> + compatible = "qcom,scm-ipq5210", "qcom,scm";
>> + };
> OP-TEE *and* SCM? What does the former do?
For OP-TEE, we have use cases like getting the random numbers,
remoteproc PAS and few others.
For SCM, setting the download mode is one typical example where OP-TEE
doesn't come into picture.
Please let me know if this helps.
>
> [...]
>
>> + soc@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
> should dma-ranges also be 36-bit?
Ack.
>
> [...]
>
>> + qupv3: geniqup@1ac0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0x0 0x01ac0000 0x0 0x2000>;
>> + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
>> + <&gcc GCC_QUPV3_AHB_SLV_CLK>;
>> + clock-names = "m-ahb", "s-ahb";
>> + ranges;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + status = "disabled";
> I see there's only a single QUP wrapper - therefore I'm going to assume
> there will never be a SoC where this needs to be disabled
Ack.
>
> [...]
>
>> +
>> + uart1: serial@1a84000 {
>> + compatible = "qcom,geni-debug-uart";
>> + reg = <0x0 0x01a84000 0x0 0x4000>;
>> + clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
>> + clock-names = "se";
>> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
> Please uniformly keep a \n before status, file-wide
Ack.
>
> Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
2026-03-16 9:03 ` Kathiravan Thirumoorthy
@ 2026-03-16 9:34 ` Konrad Dybcio
2026-03-22 5:31 ` Sumit Garg
0 siblings, 1 reply; 34+ messages in thread
From: Konrad Dybcio @ 2026-03-16 9:34 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Linus Walleij, Konrad Dybcio, Ulf Hansson,
Robert Marko, Guru Das Srinagesh, Sumit Garg
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/16/26 10:03 AM, Kathiravan Thirumoorthy wrote:
>
> On 3/13/2026 6:18 PM, Konrad Dybcio wrote:
>> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
>>> Add initial device tree support for the Qualcomm IPQ5210 SoC and
>>> rdp504 board.
>>>
>>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>>> ---
[...]
>>> + firmware {
>>> + optee {
>>> + compatible = "linaro,optee-tz";
>>> + method = "smc";
>>> + };
>>> +
>>> + scm {
>>> + compatible = "qcom,scm-ipq5210", "qcom,scm";
>>> + };
>> OP-TEE *and* SCM? What does the former do?
>
> For OP-TEE, we have use cases like getting the random numbers, remoteproc PAS and few others.
>
> For SCM, setting the download mode is one typical example where OP-TEE doesn't come into picture.
>
> Please let me know if this helps.
I think it does, but it's odd that OPTEE wouldn't handle both
fwiw +Sumit is poking at OSS firmware for other platforms and may be
interested
Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-16 8:58 ` Kathiravan Thirumoorthy
@ 2026-03-16 9:46 ` Konrad Dybcio
2026-03-16 10:58 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 34+ messages in thread
From: Konrad Dybcio @ 2026-03-16 9:46 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Linus Walleij, Konrad Dybcio, Ulf Hansson,
Robert Marko, Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/16/26 9:58 AM, Kathiravan Thirumoorthy wrote:
>
> On 3/13/2026 6:24 PM, Konrad Dybcio wrote:
>> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
>>> Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
>>> so add a driver for it.
>>>
>>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>>> ---
>> [...]
>>
>>> +static const char *const Led00_groups[] = {
>> odd uppercase
>
>
> Yeah, in HW document also only this name has the uppercase. So I just left it to align with the HW document. Do you prefer to change it to lower case to maintain consistency?
Yes, please - I would assume the original author had made a typo and
didn't really intend to have a single random occurrence of an uppercase
letter
>
>
>>
>>> + "gpio23",
>>> +};
>>> +
>>> +static const char *const led01_groups[] = {
>>> + "gpio39",
>>> +};
>>> +
>>> +static const char *const led02_groups[] = {
>>> + "gpio6",
>>> +};
>> What do these 'ledN[012]' functions represent? Are they muxes for
>> getting activity/status signals for eth/wlan ports?
>
>
> Yes, that's right. These LED functions used for the eth/wlan status.
Can we better group them, e.g. into threes in 'led[012]' functions?
(or whichever way they're coupled?)
Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver
2026-03-16 9:46 ` Konrad Dybcio
@ 2026-03-16 10:58 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 34+ messages in thread
From: Kathiravan Thirumoorthy @ 2026-03-16 10:58 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Linus Walleij, Konrad Dybcio, Ulf Hansson, Robert Marko,
Guru Das Srinagesh
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-gpio,
linux-mmc
On 3/16/2026 3:16 PM, Konrad Dybcio wrote:
> On 3/16/26 9:58 AM, Kathiravan Thirumoorthy wrote:
>> On 3/13/2026 6:24 PM, Konrad Dybcio wrote:
>>> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
>>>> Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
>>>> so add a driver for it.
>>>>
>>>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>>>> ---
>>> [...]
>>>
>>>> +static const char *const Led00_groups[] = {
>>> odd uppercase
>>
>> Yeah, in HW document also only this name has the uppercase. So I just left it to align with the HW document. Do you prefer to change it to lower case to maintain consistency?
> Yes, please - I would assume the original author had made a typo and
> didn't really intend to have a single random occurrence of an uppercase
> letter
Ack.
>
>>
>>>> + "gpio23",
>>>> +};
>>>> +
>>>> +static const char *const led01_groups[] = {
>>>> + "gpio39",
>>>> +};
>>>> +
>>>> +static const char *const led02_groups[] = {
>>>> + "gpio6",
>>>> +};
>>> What do these 'ledN[012]' functions represent? Are they muxes for
>>> getting activity/status signals for eth/wlan ports?
>>
>> Yes, that's right. These LED functions used for the eth/wlan status.
> Can we better group them, e.g. into threes in 'led[012]' functions?
> (or whichever way they're coupled?)
Ack.
>
> Konrad
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible
2026-03-11 9:45 ` [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
@ 2026-03-16 15:15 ` Ulf Hansson
1 sibling, 0 replies; 34+ messages in thread
From: Ulf Hansson @ 2026-03-16 15:15 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Walleij,
Konrad Dybcio, Robert Marko, Guru Das Srinagesh, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-gpio, linux-mmc
On Wed, 11 Mar 2026 at 10:46, Kathiravan Thirumoorthy
<kathiravan.thirumoorthy@oss.qualcomm.com> wrote:
>
> The IPQ5210 supports eMMC with an SDHCI controller. Add the appropriate
> compatible to the documentation.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> index 938be8228d668c87f0be95c63d4d951ebbadd4e4..fd1d5b04e7556903daffe86e455fde11be0dbd9f 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> @@ -38,6 +38,7 @@ properties:
> - items:
> - enum:
> - qcom,ipq5018-sdhci
> + - qcom,ipq5210-sdhci
> - qcom,ipq5332-sdhci
> - qcom,ipq5424-sdhci
> - qcom,ipq6018-sdhci
>
> --
> 2.34.1
>
Applied for next, thanks!
Kind regards
Uffe
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
2026-03-16 9:34 ` Konrad Dybcio
@ 2026-03-22 5:31 ` Sumit Garg
0 siblings, 0 replies; 34+ messages in thread
From: Sumit Garg @ 2026-03-22 5:31 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Kathiravan Thirumoorthy, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Linus Walleij, Konrad Dybcio, Ulf Hansson,
Robert Marko, Guru Das Srinagesh, linux-arm-msm, linux-clk,
devicetree, linux-kernel, linux-gpio, linux-mmc
Hey Konrad,
On Mon, Mar 16, 2026 at 3:05 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 3/16/26 10:03 AM, Kathiravan Thirumoorthy wrote:
> >
> > On 3/13/2026 6:18 PM, Konrad Dybcio wrote:
> >> On 3/11/26 10:45 AM, Kathiravan Thirumoorthy wrote:
> >>> Add initial device tree support for the Qualcomm IPQ5210 SoC and
> >>> rdp504 board.
> >>>
> >>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> >>> ---
>
> [...]
>
> >>> + firmware {
> >>> + optee {
> >>> + compatible = "linaro,optee-tz";
> >>> + method = "smc";
> >>> + };
> >>> +
> >>> + scm {
> >>> + compatible = "qcom,scm-ipq5210", "qcom,scm";
> >>> + };
> >> OP-TEE *and* SCM? What does the former do?
> >
> > For OP-TEE, we have use cases like getting the random numbers, remoteproc PAS and few others.
> >
> > For SCM, setting the download mode is one typical example where OP-TEE doesn't come into picture.
> >
> > Please let me know if this helps.
>
> I think it does, but it's odd that OPTEE wouldn't handle both
>
The SCM calls are the ones handled by TF-A which are usually referred
to as SiP SMC calls. OP-TEE doesn't handle those SiP calls but only
the SMC calls in trusted OS range. So yeah both nodes have to be
there.
> fwiw +Sumit is poking at OSS firmware for other platforms and may be
> interested
>
I think this is a WIN family chipset which only supports OP-TEE by
default. In the IoT chipsets there can either be QTEE or OP-TEE and
the bootloader (U-Boot) apply a DT fixup for OP-TEE in case it's
present.
-Sumit
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2026-03-22 5:31 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-11 9:45 [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 1/9] dt-bindings: clock: add Qualcomm IPQ5210 GCC Kathiravan Thirumoorthy
2026-03-13 13:22 ` Krzysztof Kozlowski
2026-03-16 7:16 ` Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC Kathiravan Thirumoorthy
2026-03-11 14:50 ` Dmitry Baryshkov
2026-03-13 8:42 ` Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Kathiravan Thirumoorthy
2026-03-13 13:24 ` Krzysztof Kozlowski
2026-03-16 7:18 ` Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Kathiravan Thirumoorthy
2026-03-11 14:45 ` Dmitry Baryshkov
2026-03-13 12:54 ` Konrad Dybcio
2026-03-16 8:58 ` Kathiravan Thirumoorthy
2026-03-16 9:46 ` Konrad Dybcio
2026-03-16 10:58 ` Kathiravan Thirumoorthy
2026-03-11 9:45 ` [PATCH 5/9] dt-bindings: qcom: add ipq5210 boards Kathiravan Thirumoorthy
2026-03-13 13:20 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 6/9] dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-16 15:15 ` Ulf Hansson
2026-03-11 9:45 ` [PATCH 7/9] dt-bindings: firmware: qcom,scm: Document ipq5210 SCM Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-11 9:45 ` [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Kathiravan Thirumoorthy
2026-03-13 12:48 ` Konrad Dybcio
2026-03-16 9:03 ` Kathiravan Thirumoorthy
2026-03-16 9:34 ` Konrad Dybcio
2026-03-22 5:31 ` Sumit Garg
2026-03-11 9:45 ` [PATCH 9/9] arm64: defconfig: enable IPQ5210 RDP504 base configs Kathiravan Thirumoorthy
2026-03-13 13:19 ` Krzysztof Kozlowski
2026-03-11 13:01 ` [PATCH 0/9] Add minimal boot support for Qualcomm IPQ5210 Linus Walleij
2026-03-13 6:55 ` Kathiravan Thirumoorthy
2026-03-13 13:25 ` Krzysztof Kozlowski
2026-03-16 7:27 ` Kathiravan Thirumoorthy
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