From: Adrian Hunter <adrian.hunter@intel.com>
To: Aaron Brice <aaron.brice@datasoft.com>,
ulf.hansson@linaro.org, aisheng.dong@nxp.com
Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Dave Russell <david.russell@datasoft.com>
Subject: Re: [PATCH v2] sdhci-esdhc-imx: Correct two register accesses
Date: Tue, 11 Oct 2016 12:18:20 +0300 [thread overview]
Message-ID: <4e944cda-05c6-0515-c98d-e90600f63541@intel.com> (raw)
In-Reply-To: <1476124792-18441-1-git-send-email-aaron.brice@datasoft.com>
On 10/10/16 21:39, Aaron Brice wrote:
> - The DMA error interrupt bit is in a different position as
> compared to the sdhci standard. This is accounted for in
> many cases, but not handled in the case of clearing the
> INT_STATUS register by writing a 1 to that location.
> - The HOST_CONTROL register is very different as compared to
> the sdhci standard. This is accounted for in the write
> case, but not when read back out (which it is in the sdhci
> code).
>
> Signed-off-by: Dave Russell <david.russell@datasoft.com>
> Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
> Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
next prev parent reply other threads:[~2016-10-11 9:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-10 18:39 [PATCH v2] sdhci-esdhc-imx: Correct two register accesses Aaron Brice
2016-10-11 9:18 ` Adrian Hunter [this message]
2016-10-13 7:01 ` Ulf Hansson
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