[PATCH v4 0/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[PATCH v4 0/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant
servers.  Its eMMC controller is based on the DesignWare Cores MSHC IP
(snps,dwcmshc) but requires a small set of platform-specific quirks
that cannot be expressed through the existing generic dwcmshc code
paths.

This series adds support for the 'hpe,gsc-dwcmshc' compatible:

Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the
new compatible and the mandatory 'hpe,gxp-sysreg' syscon phandle
(with register offset argument) for MSHCCS register access.  The HPE
GSC exposes only a single 'core' clock, so the clocks/clock-names
properties are constrained to a single item for this compatible.

Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c:

  * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to
    a clock mux on the GSC SoC, not a divider.  When running at
    200 MHz (HS200) freq_sel must be forced to 1 to select the correct
    high-frequency source.

  * dwcmshc_hpe_vendor_specific(): disables the command-conflict check
    and programs ATCTRL using existing AT_CTRL_* macros for reliable
    HS200 signal integrity on the GSC board topology.

  * dwcmshc_hpe_set_emmc(): helper that unconditionally sets
    DWCMSHC_CARD_IS_EMMC.  Called from both the reset and
    UHS-signaling paths.

  * dwcmshc_hpe_reset(): calls dwcmshc_reset(), re-applies vendor
    config, and calls dwcmshc_hpe_set_emmc().  The controller clears
    this bit on every reset; leaving it clear causes card-detect
    misidentification on the eMMC-only slot.

  * dwcmshc_hpe_set_uhs_signaling(): wraps dwcmshc_set_uhs_signaling()
    and calls dwcmshc_hpe_set_emmc() for all timing modes.

  * dwcmshc_hpe_gsc_init(): obtains the SoC register block and MSHCCS
    offset via the 'hpe,gxp-sysreg' syscon phandle argument and sets
    SCGSyncDis (BIT(18)) in MSHCCS to allow the HS200 RX delay lines
    to settle while the card clock is stopped.  Enables SDHCI v4 mode.

  * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
    (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN
    (preset-value registers not populated in GSC ROM).

All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF
match entry.  No existing platform (Rockchip, T-Head, sg2042, Sophgo,
etc.) has any code path change.

Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately
as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/).

Changes since v3:
  - dt-binding: Changed 'hpe,gxp-sysreg' from a bare phandle to a
    phandle-array with register offset argument, as suggested by
    Krzysztof Kozlowski.
  - dt-binding: Added else clause to disallow 'hpe,gxp-sysreg' for
    non-HPE compatibles, as suggested by Krzysztof Kozlowski.
  - dt-binding: Dropped the third example node; two are sufficient,
    as noted by Krzysztof Kozlowski.
  - Driver: Fixed multi-line comment to use the standard block comment
    style used in this file (opening '/*' on its own line), as noted
    by Adrian Hunter.
  - Driver: Added DWCMSHC_HOST_CTRL3_CMD_CONFLICT define for the
    previously bare BIT(0), as suggested by Adrian Hunter.
  - Driver: Extracted the CARD_IS_EMMC read-modify-write into a
    dwcmshc_hpe_set_emmc() helper, called from both
    dwcmshc_hpe_reset() and dwcmshc_hpe_set_uhs_signaling(), as
    suggested by Adrian Hunter.
  - Driver: Fixed regmap_update_bits() argument alignment, as noted
    by Adrian Hunter.
  - Driver: Moved HPE_GSC_MSHCCS_SCGSYNCDIS macro to the top-level
    defines section, as suggested by Shawn Lin.
  - Driver: Switched from syscon_regmap_lookup_by_phandle() with
    hardcoded offset to syscon_regmap_lookup_by_phandle_args() to
    read the MSHCCS offset from the DT phandle argument.

Changes since v2:
  - Replaced raw ATCTRL magic value 0x021f0005 with existing AT_CTRL_*
    macros and FIELD_PREP(), as suggested by Shawn Lin.
  - Refactored dwcmshc_hpe_set_uhs_signaling() to wrap
    dwcmshc_set_uhs_signaling() instead of duplicating the body,
    as suggested by Shawn Lin.
  - Dropped redundant 'maxItems: 1' from clocks and clock-names in the
    dt-binding conditional block; the items list already implies the
    count (reported by dt-review-ci / dtschema).

Changes since v1:
  - Replaced the second reg entry for MSHCCS with an 'hpe,gxp-sysreg'
    syscon phandle + regmap access, as suggested by Conor Dooley.
  - Driver now uses syscon_regmap_lookup_by_phandle() and
    regmap_update_bits() instead of devm_platform_ioremap_resource().

Nick Hawkins (2):
  dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
  mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

 .../bindings/mmc/snps,dwcmshc-sdhci.yaml      |  32 ++++
 drivers/mmc/host/sdhci-of-dwcmshc.c           | 147 ++++++++++++++++++
 2 files changed, 179 insertions(+)

-- 
2.34.1

[PATCH v4 1/2] dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
Cortex-A53) BMC SoC eMMC controller.

The HPE GSC requires access to the MSHCCS register in the SoC system
register block to configure SCG sync disable for HS200 RX delay-line
phase selection.  The required 'hpe,gxp-sysreg' property takes a
phandle to the existing 'hpe,gxp-sysreg' syscon and the MSHCCS
register offset within that block.

The HPE GSC eMMC interface only exposes a single 'core' clock (no
bus clock), so clocks/clock-names are constrained to a single item.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 .../bindings/mmc/snps,dwcmshc-sdhci.yaml      | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index 7e7c55dc2440..cf8b9b4ae5c5 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -23,6 +23,7 @@ properties:
           - const: sophgo,sg2044-dwcmshc
           - const: sophgo,sg2042-dwcmshc
       - enum:
+          - hpe,gsc-dwcmshc
           - rockchip,rk3568-dwcmshc
           - rockchip,rk3588-dwcmshc
           - snps,dwcmshc-sdhci
@@ -77,6 +78,17 @@ properties:
     description: Specifies the drive impedance in Ohm.
     enum: [33, 40, 50, 66, 100]
 
+  hpe,gxp-sysreg:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to HPE GXP SoC system register block (syscon)
+          - description: offset of the MSHCCS register within the syscon block
+    description:
+      Phandle to the HPE GXP SoC system register block (syscon) and
+      offset of the MSHCCS register used to configure clock
+      synchronisation for HS200 tuning.
+
 required:
   - compatible
   - reg
@@ -87,6 +99,26 @@ required:
 allOf:
   - $ref: mmc-controller.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: hpe,gsc-dwcmshc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: core clock
+        clock-names:
+          items:
+            - const: core
+      required:
+        - hpe,gxp-sysreg
+    else:
+      properties:
+        hpe,gxp-sysreg: false
+
   - if:
       properties:
         compatible:
-- 
2.34.1

[PATCH v4 2/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add support for the eMMC controller integrated in the HPE GSC (ARM64
Cortex-A53) BMC SoC under the new 'hpe,gsc-dwcmshc' compatible
string.

The HPE GSC eMMC controller is based on the DesignWare Cores MSHC IP
but requires several platform-specific adjustments:

Clock mux (dwcmshc_hpe_set_clock):
  The GSC SoC wires SDHCI_CLOCK_CONTROL.freq_sel directly to a clock
  mux rather than a divider.  Forcing freq_sel = 1 when the requested
  clock is 200 MHz (HS200) selects the correct high-speed clock source.
  Using the generic sdhci_set_clock() would otherwise leave the mux on
  the wrong source after tuning.

Auto-tuning / vendor config (dwcmshc_hpe_vendor_specific):
  Disables the command-conflict check (DWCMSHC_HOST_CTRL3 BIT(0)) and
  programs the ATCTRL register using existing AT_CTRL_* macros:
    AT_CTRL_AT_EN           auto-tuning circuit enable
    AT_CTRL_SWIN_TH_EN      sampling window threshold enable
    AT_CTRL_TUNE_CLK_STOP_EN tune-clock-stop enable
    PRE_CHANGE_DLY  = 3     pre-change delay
    POST_CHANGE_DLY = 3     post-change delay
    SWIN_TH_VAL    = 2      sampling window threshold
  This combination is required for reliable HS200 signal integrity on
  the GSC PCB trace topology.

eMMC mode (dwcmshc_hpe_set_emmc):
  Helper that sets DWCMSHC_CARD_IS_EMMC unconditionally.  Called from
  both the reset and UHS-signaling paths.

Reset (dwcmshc_hpe_reset):
  Calls dwcmshc_reset(), re-applies the vendor config above via
  dwcmshc_hpe_vendor_specific(), and then calls dwcmshc_hpe_set_emmc().
  The GSC controller clears the CARD_IS_EMMC bit on every reset;
  leaving it clear causes card-detect mis-identification on an
  eMMC-only slot.

UHS signaling (dwcmshc_hpe_set_uhs_signaling):
  Wraps dwcmshc_set_uhs_signaling() and calls dwcmshc_hpe_set_emmc()
  to ensure CARD_IS_EMMC is set for all timing modes, not just HS400.

Init (dwcmshc_hpe_gsc_init):
  Obtains the SoC register block and MSHCCS offset via the
  'hpe,gxp-sysreg' syscon phandle argument and sets SCGSyncDis
  (BIT(18)) to allow the HS200 RX delay lines to settle while the
  card clock is stopped during auto-tuning.  Enables SDHCI v4 mode.

Quirks:
  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN:  base clock not advertised in
    capabilities; must be obtained from the DTS 'clocks' property.
  SDHCI_QUIRK2_PRESET_VALUE_BROKEN:  preset-value registers are not
    populated in the GSC ROM.

All HPE-specific code is isolated to the new hpe_gsc_init / hpe_ops /
hpe_gsc_pdata symbols.  No existing platform (Rockchip, T-Head, sg2042,
etc.) is affected.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 147 ++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 2b75a36c096b..f4c5c1aa0ebe 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -40,7 +40,10 @@
 #define DWCMSHC_AREA1_MASK		GENMASK(11, 0)
 /* Offset inside the  vendor area 1 */
 #define DWCMSHC_HOST_CTRL3		0x8
+#define DWCMSHC_HOST_CTRL3_CMD_CONFLICT	BIT(0)
 #define DWCMSHC_EMMC_CONTROL		0x2c
+/* HPE GSC SoC MSHCCS register */
+#define HPE_GSC_MSHCCS_SCGSYNCDIS	BIT(18)
 #define DWCMSHC_CARD_IS_EMMC		BIT(0)
 #define DWCMSHC_ENHANCED_STROBE		BIT(8)
 #define DWCMSHC_EMMC_ATCTRL		0x40
@@ -1245,6 +1248,127 @@ static int sg2042_init(struct device *dev, struct sdhci_host *host,
 					     ARRAY_SIZE(clk_ids), clk_ids);
 }
 
+/*
+ * HPE GSC-specific vendor configuration: disable command conflict check
+ * and program Auto-Tuning Control register.
+ */
+static void dwcmshc_hpe_vendor_specific(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 atctrl;
+	u8 extra;
+
+	extra = sdhci_readb(host, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
+	extra &= ~DWCMSHC_HOST_CTRL3_CMD_CONFLICT;
+	sdhci_writeb(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
+
+	atctrl = AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN |
+		FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, 3) |
+		FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY) |
+		FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, 2);
+	sdhci_writel(host, atctrl, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
+}
+
+static void dwcmshc_hpe_set_emmc(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u16 ctrl;
+
+	ctrl = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
+	ctrl |= DWCMSHC_CARD_IS_EMMC;
+	sdhci_writew(host, ctrl, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
+}
+
+static void dwcmshc_hpe_reset(struct sdhci_host *host, u8 mask)
+{
+	dwcmshc_reset(host, mask);
+	dwcmshc_hpe_vendor_specific(host);
+	dwcmshc_hpe_set_emmc(host);
+}
+
+static void dwcmshc_hpe_set_uhs_signaling(struct sdhci_host *host,
+					   unsigned int timing)
+{
+	dwcmshc_set_uhs_signaling(host, timing);
+	dwcmshc_hpe_set_emmc(host);
+}
+
+/*
+ * HPE GSC eMMC controller clock setup.
+ *
+ * The GSC SoC wires the freq_sel field of SDHCI_CLOCK_CONTROL directly to a
+ * clock mux rather than a divider. Force freq_sel = 1 when running at
+ * 200 MHz (HS200) so the mux selects the correct clock source.
+ */
+static void dwcmshc_hpe_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	u16 clk;
+
+	host->mmc->actual_clock = 0;
+
+	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+	if (clock == 0)
+		return;
+
+	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+
+	if (host->mmc->actual_clock == 200000000)
+		clk |= (1 << SDHCI_DIVIDER_SHIFT);
+
+	sdhci_enable_clk(host, clk);
+}
+
+/*
+ * HPE GSC eMMC controller init.
+ *
+ * The GSC SoC requires configuring MSHCCS.  Bit 18 (SCGSyncDis) disables clock
+ * synchronisation for phase-select values going to the HS200 RX delay lines,
+ * allowing the card clock to be stopped while the delay selection settles and
+ * the phase shift is applied.  This must be used together with the ATCTRL
+ * settings programmed in dwcmshc_hpe_vendor_specific():
+ *   AT_CTRL_R.TUNE_CLK_STOP_EN  = 0x1
+ *   AT_CTRL_R.POST_CHANGE_DLY   = 0x3
+ *   AT_CTRL_R.PRE_CHANGE_DLY    = 0x3
+ *
+ * The DTS node provides a syscon phandle ('hpe,gxp-sysreg') with the
+ * MSHCCS register offset as an argument.
+ */
+static int dwcmshc_hpe_gsc_init(struct device *dev, struct sdhci_host *host,
+				struct dwcmshc_priv *dwc_priv)
+{
+	unsigned int reg_offset;
+	struct regmap *soc_ctrl;
+	int ret;
+
+	/* Disable cmd conflict check and configure auto-tuning */
+	dwcmshc_hpe_vendor_specific(host);
+
+	/* Look up the GXP sysreg syscon and MSHCCS offset */
+	soc_ctrl = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+							"hpe,gxp-sysreg",
+							1, &reg_offset);
+	if (IS_ERR(soc_ctrl)) {
+		dev_err(dev, "failed to get hpe,gxp-sysreg syscon\n");
+		return PTR_ERR(soc_ctrl);
+	}
+
+	/* Set SCGSyncDis (bit 18) to disable sync on HS200 RX delay lines */
+	ret = regmap_update_bits(soc_ctrl, reg_offset,
+				 HPE_GSC_MSHCCS_SCGSYNCDIS,
+				 HPE_GSC_MSHCCS_SCGSYNCDIS);
+	if (ret) {
+		dev_err(dev, "failed to set SCGSyncDis in MSHCCS\n");
+		return ret;
+	}
+
+	sdhci_enable_v4_mode(host);
+
+	return 0;
+}
+
 static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int clock)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -1834,6 +1958,25 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = {
 	.init = eic7700_init,
 };
 
+static const struct sdhci_ops sdhci_dwcmshc_hpe_ops = {
+	.set_clock		= dwcmshc_hpe_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.set_uhs_signaling	= dwcmshc_hpe_set_uhs_signaling,
+	.get_max_clock		= dwcmshc_get_max_clock,
+	.reset			= dwcmshc_hpe_reset,
+	.adma_write_desc	= dwcmshc_adma_write_desc,
+	.irq			= dwcmshc_cqe_irq_handler,
+};
+
+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_hpe_gsc_pdata = {
+	.pdata = {
+		.ops = &sdhci_dwcmshc_hpe_ops,
+		.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+		.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+	},
+	.init = dwcmshc_hpe_gsc_init,
+};
+
 static const struct cqhci_host_ops dwcmshc_cqhci_ops = {
 	.enable		= dwcmshc_sdhci_cqe_enable,
 	.disable	= sdhci_cqe_disable,
@@ -1942,6 +2085,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
 		.compatible = "eswin,eic7700-dwcmshc",
 		.data = &sdhci_dwcmshc_eic7700_pdata,
 	},
+	{
+		.compatible = "hpe,gsc-dwcmshc",
+		.data = &sdhci_dwcmshc_hpe_gsc_pdata,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
-- 
2.34.1

Re: [PATCH v4 1/2] dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible

[Krzysztof Kozlowski]

On Mon, Mar 16, 2026 at 10:01:14AM -0500, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
> Cortex-A53) BMC SoC eMMC controller.
> 
> The HPE GSC requires access to the MSHCCS register in the SoC system
> register block to configure SCG sync disable for HS200 RX delay-line
> phase selection.  The required 'hpe,gxp-sysreg' property takes a
> phandle to the existing 'hpe,gxp-sysreg' syscon and the MSHCCS
> register offset within that block.
> 
> The HPE GSC eMMC interface only exposes a single 'core' clock (no
> bus clock), so clocks/clock-names are constrained to a single item.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
>  .../bindings/mmc/snps,dwcmshc-sdhci.yaml      | 32 +++++++++++++++++++
>  1 file changed, 32 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v4 2/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[Adrian Hunter]

On 16/03/2026 17:01, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add support for the eMMC controller integrated in the HPE GSC (ARM64
> Cortex-A53) BMC SoC under the new 'hpe,gsc-dwcmshc' compatible
> string.
> 
> The HPE GSC eMMC controller is based on the DesignWare Cores MSHC IP
> but requires several platform-specific adjustments:
> 
> Clock mux (dwcmshc_hpe_set_clock):
>   The GSC SoC wires SDHCI_CLOCK_CONTROL.freq_sel directly to a clock
>   mux rather than a divider.  Forcing freq_sel = 1 when the requested
>   clock is 200 MHz (HS200) selects the correct high-speed clock source.
>   Using the generic sdhci_set_clock() would otherwise leave the mux on
>   the wrong source after tuning.
> 
> Auto-tuning / vendor config (dwcmshc_hpe_vendor_specific):
>   Disables the command-conflict check (DWCMSHC_HOST_CTRL3 BIT(0)) and
>   programs the ATCTRL register using existing AT_CTRL_* macros:
>     AT_CTRL_AT_EN           auto-tuning circuit enable
>     AT_CTRL_SWIN_TH_EN      sampling window threshold enable
>     AT_CTRL_TUNE_CLK_STOP_EN tune-clock-stop enable
>     PRE_CHANGE_DLY  = 3     pre-change delay
>     POST_CHANGE_DLY = 3     post-change delay
>     SWIN_TH_VAL    = 2      sampling window threshold
>   This combination is required for reliable HS200 signal integrity on
>   the GSC PCB trace topology.
> 
> eMMC mode (dwcmshc_hpe_set_emmc):
>   Helper that sets DWCMSHC_CARD_IS_EMMC unconditionally.  Called from
>   both the reset and UHS-signaling paths.
> 
> Reset (dwcmshc_hpe_reset):
>   Calls dwcmshc_reset(), re-applies the vendor config above via
>   dwcmshc_hpe_vendor_specific(), and then calls dwcmshc_hpe_set_emmc().
>   The GSC controller clears the CARD_IS_EMMC bit on every reset;
>   leaving it clear causes card-detect mis-identification on an
>   eMMC-only slot.
> 
> UHS signaling (dwcmshc_hpe_set_uhs_signaling):
>   Wraps dwcmshc_set_uhs_signaling() and calls dwcmshc_hpe_set_emmc()
>   to ensure CARD_IS_EMMC is set for all timing modes, not just HS400.
> 
> Init (dwcmshc_hpe_gsc_init):
>   Obtains the SoC register block and MSHCCS offset via the
>   'hpe,gxp-sysreg' syscon phandle argument and sets SCGSyncDis
>   (BIT(18)) to allow the HS200 RX delay lines to settle while the
>   card clock is stopped during auto-tuning.  Enables SDHCI v4 mode.
> 
> Quirks:
>   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN:  base clock not advertised in
>     capabilities; must be obtained from the DTS 'clocks' property.
>   SDHCI_QUIRK2_PRESET_VALUE_BROKEN:  preset-value registers are not
>     populated in the GSC ROM.
> 
> All HPE-specific code is isolated to the new hpe_gsc_init / hpe_ops /
> hpe_gsc_pdata symbols.  No existing platform (Rockchip, T-Head, sg2042,
> etc.) is affected.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

If you re-spin, there is 1 cosmetic comment below.  Otherwise:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 147 ++++++++++++++++++++++++++++
>  1 file changed, 147 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 2b75a36c096b..f4c5c1aa0ebe 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -40,7 +40,10 @@
>  #define DWCMSHC_AREA1_MASK		GENMASK(11, 0)
>  /* Offset inside the  vendor area 1 */
>  #define DWCMSHC_HOST_CTRL3		0x8
> +#define DWCMSHC_HOST_CTRL3_CMD_CONFLICT	BIT(0)
>  #define DWCMSHC_EMMC_CONTROL		0x2c
> +/* HPE GSC SoC MSHCCS register */
> +#define HPE_GSC_MSHCCS_SCGSYNCDIS	BIT(18)
>  #define DWCMSHC_CARD_IS_EMMC		BIT(0)
>  #define DWCMSHC_ENHANCED_STROBE		BIT(8)
>  #define DWCMSHC_EMMC_ATCTRL		0x40
> @@ -1245,6 +1248,127 @@ static int sg2042_init(struct device *dev, struct sdhci_host *host,
>  					     ARRAY_SIZE(clk_ids), clk_ids);
>  }
>  
> +/*
> + * HPE GSC-specific vendor configuration: disable command conflict check
> + * and program Auto-Tuning Control register.
> + */
> +static void dwcmshc_hpe_vendor_specific(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
> +	u32 atctrl;
> +	u8 extra;
> +
> +	extra = sdhci_readb(host, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
> +	extra &= ~DWCMSHC_HOST_CTRL3_CMD_CONFLICT;
> +	sdhci_writeb(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
> +
> +	atctrl = AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN |
> +		FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, 3) |
> +		FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY) |
> +		FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, 2);
> +	sdhci_writel(host, atctrl, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
> +}
> +
> +static void dwcmshc_hpe_set_emmc(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
> +	u16 ctrl;
> +
> +	ctrl = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
> +	ctrl |= DWCMSHC_CARD_IS_EMMC;
> +	sdhci_writew(host, ctrl, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
> +}
> +
> +static void dwcmshc_hpe_reset(struct sdhci_host *host, u8 mask)
> +{
> +	dwcmshc_reset(host, mask);
> +	dwcmshc_hpe_vendor_specific(host);
> +	dwcmshc_hpe_set_emmc(host);
> +}
> +
> +static void dwcmshc_hpe_set_uhs_signaling(struct sdhci_host *host,
> +					   unsigned int timing)

Unnecessary line wrap

> +{
> +	dwcmshc_set_uhs_signaling(host, timing);
> +	dwcmshc_hpe_set_emmc(host);
> +}
> +
> +/*
> + * HPE GSC eMMC controller clock setup.
> + *
> + * The GSC SoC wires the freq_sel field of SDHCI_CLOCK_CONTROL directly to a
> + * clock mux rather than a divider. Force freq_sel = 1 when running at
> + * 200 MHz (HS200) so the mux selects the correct clock source.
> + */
> +static void dwcmshc_hpe_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> +	u16 clk;
> +
> +	host->mmc->actual_clock = 0;
> +
> +	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +
> +	if (clock == 0)
> +		return;
> +
> +	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
> +
> +	if (host->mmc->actual_clock == 200000000)
> +		clk |= (1 << SDHCI_DIVIDER_SHIFT);
> +
> +	sdhci_enable_clk(host, clk);
> +}
> +
> +/*
> + * HPE GSC eMMC controller init.
> + *
> + * The GSC SoC requires configuring MSHCCS.  Bit 18 (SCGSyncDis) disables clock
> + * synchronisation for phase-select values going to the HS200 RX delay lines,
> + * allowing the card clock to be stopped while the delay selection settles and
> + * the phase shift is applied.  This must be used together with the ATCTRL
> + * settings programmed in dwcmshc_hpe_vendor_specific():
> + *   AT_CTRL_R.TUNE_CLK_STOP_EN  = 0x1
> + *   AT_CTRL_R.POST_CHANGE_DLY   = 0x3
> + *   AT_CTRL_R.PRE_CHANGE_DLY    = 0x3
> + *
> + * The DTS node provides a syscon phandle ('hpe,gxp-sysreg') with the
> + * MSHCCS register offset as an argument.
> + */
> +static int dwcmshc_hpe_gsc_init(struct device *dev, struct sdhci_host *host,
> +				struct dwcmshc_priv *dwc_priv)
> +{
> +	unsigned int reg_offset;
> +	struct regmap *soc_ctrl;
> +	int ret;
> +
> +	/* Disable cmd conflict check and configure auto-tuning */
> +	dwcmshc_hpe_vendor_specific(host);
> +
> +	/* Look up the GXP sysreg syscon and MSHCCS offset */
> +	soc_ctrl = syscon_regmap_lookup_by_phandle_args(dev->of_node,
> +							"hpe,gxp-sysreg",
> +							1, &reg_offset);
> +	if (IS_ERR(soc_ctrl)) {
> +		dev_err(dev, "failed to get hpe,gxp-sysreg syscon\n");
> +		return PTR_ERR(soc_ctrl);
> +	}
> +
> +	/* Set SCGSyncDis (bit 18) to disable sync on HS200 RX delay lines */
> +	ret = regmap_update_bits(soc_ctrl, reg_offset,
> +				 HPE_GSC_MSHCCS_SCGSYNCDIS,
> +				 HPE_GSC_MSHCCS_SCGSYNCDIS);
> +	if (ret) {
> +		dev_err(dev, "failed to set SCGSyncDis in MSHCCS\n");
> +		return ret;
> +	}
> +
> +	sdhci_enable_v4_mode(host);
> +
> +	return 0;
> +}
> +
>  static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int clock)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -1834,6 +1958,25 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = {
>  	.init = eic7700_init,
>  };
>  
> +static const struct sdhci_ops sdhci_dwcmshc_hpe_ops = {
> +	.set_clock		= dwcmshc_hpe_set_clock,
> +	.set_bus_width		= sdhci_set_bus_width,
> +	.set_uhs_signaling	= dwcmshc_hpe_set_uhs_signaling,
> +	.get_max_clock		= dwcmshc_get_max_clock,
> +	.reset			= dwcmshc_hpe_reset,
> +	.adma_write_desc	= dwcmshc_adma_write_desc,
> +	.irq			= dwcmshc_cqe_irq_handler,
> +};
> +
> +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_hpe_gsc_pdata = {
> +	.pdata = {
> +		.ops = &sdhci_dwcmshc_hpe_ops,
> +		.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +		.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> +	},
> +	.init = dwcmshc_hpe_gsc_init,
> +};
> +
>  static const struct cqhci_host_ops dwcmshc_cqhci_ops = {
>  	.enable		= dwcmshc_sdhci_cqe_enable,
>  	.disable	= sdhci_cqe_disable,
> @@ -1942,6 +2085,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
>  		.compatible = "eswin,eic7700-dwcmshc",
>  		.data = &sdhci_dwcmshc_eic7700_pdata,
>  	},
> +	{
> +		.compatible = "hpe,gsc-dwcmshc",
> +		.data = &sdhci_dwcmshc_hpe_gsc_pdata,
> +	},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);

Re: [PATCH v4 0/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[Ulf Hansson]

On Mon, 16 Mar 2026 at 16:01, <nick.hawkins@hpe.com> wrote:
>
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant
> servers.  Its eMMC controller is based on the DesignWare Cores MSHC IP
> (snps,dwcmshc) but requires a small set of platform-specific quirks
> that cannot be expressed through the existing generic dwcmshc code
> paths.
>
> This series adds support for the 'hpe,gsc-dwcmshc' compatible:
>
> Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the
> new compatible and the mandatory 'hpe,gxp-sysreg' syscon phandle
> (with register offset argument) for MSHCCS register access.  The HPE
> GSC exposes only a single 'core' clock, so the clocks/clock-names
> properties are constrained to a single item for this compatible.
>
> Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c:
>
>   * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to
>     a clock mux on the GSC SoC, not a divider.  When running at
>     200 MHz (HS200) freq_sel must be forced to 1 to select the correct
>     high-frequency source.
>
>   * dwcmshc_hpe_vendor_specific(): disables the command-conflict check
>     and programs ATCTRL using existing AT_CTRL_* macros for reliable
>     HS200 signal integrity on the GSC board topology.
>
>   * dwcmshc_hpe_set_emmc(): helper that unconditionally sets
>     DWCMSHC_CARD_IS_EMMC.  Called from both the reset and
>     UHS-signaling paths.
>
>   * dwcmshc_hpe_reset(): calls dwcmshc_reset(), re-applies vendor
>     config, and calls dwcmshc_hpe_set_emmc().  The controller clears
>     this bit on every reset; leaving it clear causes card-detect
>     misidentification on the eMMC-only slot.
>
>   * dwcmshc_hpe_set_uhs_signaling(): wraps dwcmshc_set_uhs_signaling()
>     and calls dwcmshc_hpe_set_emmc() for all timing modes.
>
>   * dwcmshc_hpe_gsc_init(): obtains the SoC register block and MSHCCS
>     offset via the 'hpe,gxp-sysreg' syscon phandle argument and sets
>     SCGSyncDis (BIT(18)) in MSHCCS to allow the HS200 RX delay lines
>     to settle while the card clock is stopped.  Enables SDHCI v4 mode.
>
>   * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
>     (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN
>     (preset-value registers not populated in GSC ROM).
>
> All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF
> match entry.  No existing platform (Rockchip, T-Head, sg2042, Sophgo,
> etc.) has any code path change.
>
> Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately
> as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/).
>
> Changes since v3:
>   - dt-binding: Changed 'hpe,gxp-sysreg' from a bare phandle to a
>     phandle-array with register offset argument, as suggested by
>     Krzysztof Kozlowski.
>   - dt-binding: Added else clause to disallow 'hpe,gxp-sysreg' for
>     non-HPE compatibles, as suggested by Krzysztof Kozlowski.
>   - dt-binding: Dropped the third example node; two are sufficient,
>     as noted by Krzysztof Kozlowski.
>   - Driver: Fixed multi-line comment to use the standard block comment
>     style used in this file (opening '/*' on its own line), as noted
>     by Adrian Hunter.
>   - Driver: Added DWCMSHC_HOST_CTRL3_CMD_CONFLICT define for the
>     previously bare BIT(0), as suggested by Adrian Hunter.
>   - Driver: Extracted the CARD_IS_EMMC read-modify-write into a
>     dwcmshc_hpe_set_emmc() helper, called from both
>     dwcmshc_hpe_reset() and dwcmshc_hpe_set_uhs_signaling(), as
>     suggested by Adrian Hunter.
>   - Driver: Fixed regmap_update_bits() argument alignment, as noted
>     by Adrian Hunter.
>   - Driver: Moved HPE_GSC_MSHCCS_SCGSYNCDIS macro to the top-level
>     defines section, as suggested by Shawn Lin.
>   - Driver: Switched from syscon_regmap_lookup_by_phandle() with
>     hardcoded offset to syscon_regmap_lookup_by_phandle_args() to
>     read the MSHCCS offset from the DT phandle argument.
>
> Changes since v2:
>   - Replaced raw ATCTRL magic value 0x021f0005 with existing AT_CTRL_*
>     macros and FIELD_PREP(), as suggested by Shawn Lin.
>   - Refactored dwcmshc_hpe_set_uhs_signaling() to wrap
>     dwcmshc_set_uhs_signaling() instead of duplicating the body,
>     as suggested by Shawn Lin.
>   - Dropped redundant 'maxItems: 1' from clocks and clock-names in the
>     dt-binding conditional block; the items list already implies the
>     count (reported by dt-review-ci / dtschema).
>
> Changes since v1:
>   - Replaced the second reg entry for MSHCCS with an 'hpe,gxp-sysreg'
>     syscon phandle + regmap access, as suggested by Conor Dooley.
>   - Driver now uses syscon_regmap_lookup_by_phandle() and
>     regmap_update_bits() instead of devm_platform_ioremap_resource().
>
> Nick Hawkins (2):
>   dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
>   mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support
>
>  .../bindings/mmc/snps,dwcmshc-sdhci.yaml      |  32 ++++
>  drivers/mmc/host/sdhci-of-dwcmshc.c           | 147 ++++++++++++++++++
>  2 files changed, 179 insertions(+)
>
> --
> 2.34.1
>

The series applied for next, thanks!

Note that, I amended patch2 according to Adrian's comment.

Kind regards
Uffe