* [PATCH v1 0/3] Enable emmc and SD on QCS615
@ 2024-10-23 9:27 Yuanjie Yang
2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Yuanjie Yang @ 2024-10-23 9:27 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson,
konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz,
Yuanjie Yang
Add SD and emmc support to the QCS615 Ride platform. The SD controller
and emmc controller of QCS615 are derived from SM6115. Include the
relevant binding documents accordingly. Additionally, configure emmc-related
and SD-related opp, power, and interconnect settings in the device tree.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
This patch series depends on below patch series:
https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/
https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/
Yuanjie Yang (3):
dt-bindings: mmc: Add sdhci compatible for QCS615
arm64: dts: qcom: qcs615: add SD and emmc node
arm64: dts: qcom: qcs615-ride: Enable SD and emmc node
.../devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 31 +++
arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 ++++++++++++++++++
3 files changed, 230 insertions(+)
--
2.34.1
Thanks,
Yuanjie
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 2024-10-23 9:27 [PATCH v1 0/3] Enable emmc and SD on QCS615 Yuanjie Yang @ 2024-10-23 9:27 ` Yuanjie Yang 2024-10-24 7:39 ` Krzysztof Kozlowski 2024-10-25 14:51 ` Ulf Hansson 2024-10-23 9:27 ` [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 3/3] arm64: dts: qcom: qcs615-ride: Enable " Yuanjie Yang 2 siblings, 2 replies; 10+ messages in thread From: Yuanjie Yang @ 2024-10-23 9:27 UTC (permalink / raw) To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz, Yuanjie Yang Document the sdhci compatible for Qualcomm QCS615 to support function for emmc and sd card on the Soc. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index b32253c60919..164a45cdb972 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -43,6 +43,7 @@ properties: - qcom,ipq9574-sdhci - qcom,qcm2290-sdhci - qcom,qcs404-sdhci + - qcom,qcs615-sdhci - qcom,qdu1000-sdhci - qcom,sc7180-sdhci - qcom,sc7280-sdhci -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang @ 2024-10-24 7:39 ` Krzysztof Kozlowski 2024-10-25 14:51 ` Ulf Hansson 1 sibling, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2024-10-24 7:39 UTC (permalink / raw) To: Yuanjie Yang Cc: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio, linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz On Wed, Oct 23, 2024 at 05:27:06PM +0800, Yuanjie Yang wrote: > Document the sdhci compatible for Qualcomm QCS615 to support > function for emmc and sd card on the Soc. > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang 2024-10-24 7:39 ` Krzysztof Kozlowski @ 2024-10-25 14:51 ` Ulf Hansson 1 sibling, 0 replies; 10+ messages in thread From: Ulf Hansson @ 2024-10-25 14:51 UTC (permalink / raw) To: Yuanjie Yang Cc: robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio, linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz On Wed, 23 Oct 2024 at 11:28, Yuanjie Yang <quic_yuanjiey@quicinc.com> wrote: > > Document the sdhci compatible for Qualcomm QCS615 to support > function for emmc and sd card on the Soc. > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > index b32253c60919..164a45cdb972 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > @@ -43,6 +43,7 @@ properties: > - qcom,ipq9574-sdhci > - qcom,qcm2290-sdhci > - qcom,qcs404-sdhci > + - qcom,qcs615-sdhci > - qcom,qdu1000-sdhci > - qcom,sc7180-sdhci > - qcom,sc7280-sdhci > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node 2024-10-23 9:27 [PATCH v1 0/3] Enable emmc and SD on QCS615 Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang @ 2024-10-23 9:27 ` Yuanjie Yang 2024-10-24 20:42 ` Dmitry Baryshkov 2024-10-23 9:27 ` [PATCH v1 3/3] arm64: dts: qcom: qcs615-ride: Enable " Yuanjie Yang 2 siblings, 1 reply; 10+ messages in thread From: Yuanjie Yang @ 2024-10-23 9:27 UTC (permalink / raw) To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz, Yuanjie Yang Add SD and emmc support to the QCS615 Ride platform. The SD controller and emmc controller of QCS615 are derived from SM6115. Include the relevant binding documents accordingly. Additionally, configure emmc-related and SD-related opp, power, and interconnect settings in the device tree. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index fcba83fca7cf..3840edf13fe8 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -399,6 +399,65 @@ qfprom: efuse@780000 { #size-cells = <1>; }; + sdhc_1: mmc@7c4000 { + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x7c4000 0 0x1000>, + <0 0x7c5000 0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", + "core", + "xo", + "ice"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + iommus = <&apps_smmu 0x02c0 0x0>; + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + bus-width = <8>; + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + supports-cqe; + dma-coherent; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x8c0000 0x0 0x6000>; @@ -494,6 +553,145 @@ qup_uart0_rx: qup-uart0-rx-state { pins = "gpio17"; function = "qup0"; }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5"; + reg = <0x0 0x8804000 0x0 0x1000>; + reg-names = "hc"; + + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x02a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + dma-coherent; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; dc_noc: interconnect@9160000 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node 2024-10-23 9:27 ` [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node Yuanjie Yang @ 2024-10-24 20:42 ` Dmitry Baryshkov 2024-10-25 2:59 ` Yuanjie Yang 0 siblings, 1 reply; 10+ messages in thread From: Dmitry Baryshkov @ 2024-10-24 20:42 UTC (permalink / raw) To: Yuanjie Yang Cc: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio, linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz On Wed, Oct 23, 2024 at 05:27:07PM +0800, Yuanjie Yang wrote: > Add SD and emmc support to the QCS615 Ride platform. The SD controller > and emmc controller of QCS615 are derived from SM6115. Include the > relevant binding documents accordingly. Additionally, configure > emmc-related and SD-related opp, power, and interconnect settings > in the device tree. > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > 1 file changed, 198 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index fcba83fca7cf..3840edf13fe8 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > #size-cells = <1>; > }; > > + sdhc_1: mmc@7c4000 { > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0 0x7c4000 0 0x1000>, > + <0 0x7c5000 0 0x1000>; <0x0 0x007c4000 0x0 0x1000> (this applies to all address nodes, so sdhc_2 too. > + reg-names = "hc", > + "cqhci"; > + > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", > + "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > + clock-names = "iface", > + "core", > + "xo", > + "ice"; > + > + resets = <&gcc GCC_SDCC1_BCR>; > + > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc1_opp_table>; > + iommus = <&apps_smmu 0x02c0 0x0>; > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; > + > + bus-width = <8>; > + qcom,dll-config = <0x000f642c>; > + qcom,ddr-config = <0x80040868>; > + supports-cqe; > + dma-coherent; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + mmc-hs400-enhanced-strobe; Are these board properties or SoC properties? > + status = "disabled"; > + -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node 2024-10-24 20:42 ` Dmitry Baryshkov @ 2024-10-25 2:59 ` Yuanjie Yang 2024-10-25 5:48 ` Dmitry Baryshkov 0 siblings, 1 reply; 10+ messages in thread From: Yuanjie Yang @ 2024-10-25 2:59 UTC (permalink / raw) To: Dmitry Baryshkov, ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz, quic_yuanjiey On Thu, Oct 24, 2024 at 11:42:26PM +0300, Dmitry Baryshkov wrote: > On Wed, Oct 23, 2024 at 05:27:07PM +0800, Yuanjie Yang wrote: > > Add SD and emmc support to the QCS615 Ride platform. The SD controller > > and emmc controller of QCS615 are derived from SM6115. Include the > > relevant binding documents accordingly. Additionally, configure > > emmc-related and SD-related opp, power, and interconnect settings > > in the device tree. > > > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > 1 file changed, 198 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > index fcba83fca7cf..3840edf13fe8 100644 > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > > #size-cells = <1>; > > }; > > > > + sdhc_1: mmc@7c4000 { > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0 0x7c4000 0 0x1000>, > > + <0 0x7c5000 0 0x1000>; > > <0x0 0x007c4000 0x0 0x1000> (this applies to all address nodes, so > sdhc_2 too. Thanks, in the next version, I will adjust all the values in the reg to hexadecimal. > > > + reg-names = "hc", > > + "cqhci"; > > + > > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "hc_irq", > > + "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > + <&gcc GCC_SDCC1_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>, > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > + clock-names = "iface", > > + "core", > > + "xo", > > + "ice"; > > + > > + resets = <&gcc GCC_SDCC1_BCR>; > > + > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc1_opp_table>; > > + iommus = <&apps_smmu 0x02c0 0x0>; > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "sdhc-ddr", > > + "cpu-sdhc"; > > + > > + bus-width = <8>; > > + qcom,dll-config = <0x000f642c>; > > + qcom,ddr-config = <0x80040868>; > > + supports-cqe; > > + dma-coherent; > > + mmc-ddr-1_8v; > > + mmc-hs200-1_8v; > > + mmc-hs400-1_8v; > > + mmc-hs400-enhanced-strobe; > > Are these board properties or SoC properties? Thanks, these properties are Soc properties, so I put them in dtsi. > > + status = "disabled"; > > + > > -- > With best wishes > Dmitry Thanks, Yuanjie ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node 2024-10-25 2:59 ` Yuanjie Yang @ 2024-10-25 5:48 ` Dmitry Baryshkov 2024-10-25 6:30 ` Yuanjie Yang 0 siblings, 1 reply; 10+ messages in thread From: Dmitry Baryshkov @ 2024-10-25 5:48 UTC (permalink / raw) To: Yuanjie Yang Cc: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio, linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz On Fri, 25 Oct 2024 at 06:00, Yuanjie Yang <quic_yuanjiey@quicinc.com> wrote: > > On Thu, Oct 24, 2024 at 11:42:26PM +0300, Dmitry Baryshkov wrote: > > On Wed, Oct 23, 2024 at 05:27:07PM +0800, Yuanjie Yang wrote: > > > Add SD and emmc support to the QCS615 Ride platform. The SD controller > > > and emmc controller of QCS615 are derived from SM6115. Include the > > > relevant binding documents accordingly. Additionally, configure > > > emmc-related and SD-related opp, power, and interconnect settings > > > in the device tree. > > > > > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > > > --- > > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > > 1 file changed, 198 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > index fcba83fca7cf..3840edf13fe8 100644 > > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > > > #size-cells = <1>; > > > }; > > > > > > + sdhc_1: mmc@7c4000 { > > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > > + reg = <0 0x7c4000 0 0x1000>, > > > + <0 0x7c5000 0 0x1000>; > > > > <0x0 0x007c4000 0x0 0x1000> (this applies to all address nodes, so > > sdhc_2 too. > Thanks, in the next version, I will adjust all the values in the reg to hexadecimal. Not only that. In the entry that I've posted there is a second change. > > > > > > + reg-names = "hc", > > > + "cqhci"; > > > + > > > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "hc_irq", > > > + "pwr_irq"; > > > + > > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > > + <&gcc GCC_SDCC1_APPS_CLK>, > > > + <&rpmhcc RPMH_CXO_CLK>, > > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > > + clock-names = "iface", > > > + "core", > > > + "xo", > > > + "ice"; > > > + > > > + resets = <&gcc GCC_SDCC1_BCR>; > > > + > > > + power-domains = <&rpmhpd RPMHPD_CX>; > > > + operating-points-v2 = <&sdhc1_opp_table>; > > > + iommus = <&apps_smmu 0x02c0 0x0>; > > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > > + interconnect-names = "sdhc-ddr", > > > + "cpu-sdhc"; > > > + > > > + bus-width = <8>; > > > + qcom,dll-config = <0x000f642c>; > > > + qcom,ddr-config = <0x80040868>; > > > + supports-cqe; > > > + dma-coherent; > > > + mmc-ddr-1_8v; > > > + mmc-hs200-1_8v; > > > + mmc-hs400-1_8v; > > > + mmc-hs400-enhanced-strobe; > > > > Are these board properties or SoC properties? > Thanks, these properties are Soc properties, so I put them in dtsi. > > > > + status = "disabled"; > > > + > > > > -- > > With best wishes > > Dmitry > > Thanks, > Yuanjie -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node 2024-10-25 5:48 ` Dmitry Baryshkov @ 2024-10-25 6:30 ` Yuanjie Yang 0 siblings, 0 replies; 10+ messages in thread From: Yuanjie Yang @ 2024-10-25 6:30 UTC (permalink / raw) To: Dmitry Baryshkov, ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz, quic_yuanjiey On Fri, Oct 25, 2024 at 08:48:48AM +0300, Dmitry Baryshkov wrote: > On Fri, 25 Oct 2024 at 06:00, Yuanjie Yang <quic_yuanjiey@quicinc.com> wrote: > > > > On Thu, Oct 24, 2024 at 11:42:26PM +0300, Dmitry Baryshkov wrote: > > > On Wed, Oct 23, 2024 at 05:27:07PM +0800, Yuanjie Yang wrote: > > > > Add SD and emmc support to the QCS615 Ride platform. The SD controller > > > > and emmc controller of QCS615 are derived from SM6115. Include the > > > > relevant binding documents accordingly. Additionally, configure > > > > emmc-related and SD-related opp, power, and interconnect settings > > > > in the device tree. > > > > > > > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > > > > --- > > > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > > > 1 file changed, 198 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > > index fcba83fca7cf..3840edf13fe8 100644 > > > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > > > > #size-cells = <1>; > > > > }; > > > > > > > > + sdhc_1: mmc@7c4000 { > > > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > > > + reg = <0 0x7c4000 0 0x1000>, > > > > + <0 0x7c5000 0 0x1000>; > > > > > > <0x0 0x007c4000 0x0 0x1000> (this applies to all address nodes, so > > > sdhc_2 too. > > Thanks, in the next version, I will adjust all the values in the reg to hexadecimal. > > Not only that. In the entry that I've posted there is a second change. Thanks, of course, in the next version I will change all the values in the reg of sdhc1 and sdhc2 to hexadecimal.I will also check other places to see if there are similar situations that need to be modified. > > > > > > > > > + reg-names = "hc", > > > > + "cqhci"; > > > > + > > > > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "hc_irq", > > > > + "pwr_irq"; > > > > + > > > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > > > + <&gcc GCC_SDCC1_APPS_CLK>, > > > > + <&rpmhcc RPMH_CXO_CLK>, > > > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > > > + clock-names = "iface", > > > > + "core", > > > > + "xo", > > > > + "ice"; > > > > + > > > > + resets = <&gcc GCC_SDCC1_BCR>; > > > > + > > > > + power-domains = <&rpmhpd RPMHPD_CX>; > > > > + operating-points-v2 = <&sdhc1_opp_table>; > > > > + iommus = <&apps_smmu 0x02c0 0x0>; > > > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > > > + interconnect-names = "sdhc-ddr", > > > > + "cpu-sdhc"; > > > > + > > > > + bus-width = <8>; > > > > + qcom,dll-config = <0x000f642c>; > > > > + qcom,ddr-config = <0x80040868>; > > > > + supports-cqe; > > > > + dma-coherent; > > > > + mmc-ddr-1_8v; > > > > + mmc-hs200-1_8v; > > > > + mmc-hs400-1_8v; > > > > + mmc-hs400-enhanced-strobe; > > > > > > Are these board properties or SoC properties? > > Thanks, these properties are Soc properties, so I put them in dtsi. > > > > > > + status = "disabled"; > > > > + > > > > > > -- > > > With best wishes > > > Dmitry > > > > Thanks, > > Yuanjie > > > > -- > With best wishes > Dmitry Thanks, Yuanjie ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 3/3] arm64: dts: qcom: qcs615-ride: Enable SD and emmc node 2024-10-23 9:27 [PATCH v1 0/3] Enable emmc and SD on QCS615 Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node Yuanjie Yang @ 2024-10-23 9:27 ` Yuanjie Yang 2 siblings, 0 replies; 10+ messages in thread From: Yuanjie Yang @ 2024-10-23 9:27 UTC (permalink / raw) To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson, konradybcio Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz, Yuanjie Yang Enable SD and emmc on the Qualcomm QCS615 Ride platform. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 4ef969a6af15..7a5d0a3e725c 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/gpio/gpio.h> #include "qcs615.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; @@ -12,6 +13,8 @@ / { chassis-type = "embedded"; aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; serial0 = &uart0; }; @@ -213,6 +216,34 @@ &rpmhcc { clocks = <&xo_board_clk>; }; +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l17a>; + vqmmc-supply = <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l10a>; + vqmmc-supply = <&vreg_l2a>; + + status = "okay"; +}; + &uart0 { status = "okay"; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-10-25 14:52 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-10-23 9:27 [PATCH v1 0/3] Enable emmc and SD on QCS615 Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 1/3] dt-bindings: mmc: Add sdhci compatible for QCS615 Yuanjie Yang 2024-10-24 7:39 ` Krzysztof Kozlowski 2024-10-25 14:51 ` Ulf Hansson 2024-10-23 9:27 ` [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node Yuanjie Yang 2024-10-24 20:42 ` Dmitry Baryshkov 2024-10-25 2:59 ` Yuanjie Yang 2024-10-25 5:48 ` Dmitry Baryshkov 2024-10-25 6:30 ` Yuanjie Yang 2024-10-23 9:27 ` [PATCH v1 3/3] arm64: dts: qcom: qcs615-ride: Enable " Yuanjie Yang
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