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From: "mar.krzeminski" <mar.krzeminski@gmail.com>
To: Marek Vasut <marek.vasut@gmail.com>,
	cyrille.pitchen@atmel.com, linux-mtd@lists.infradead.org
Cc: dwmw2@infradead.org, computersforpeace@gmail.com,
	boris.brezillon@free-electrons.com
Subject: Re: [PATCH v4 1/2] mtd: spi-nor: Fix whole chip erasing for stacked chips.
Date: Sat, 7 Jan 2017 23:33:43 +0100	[thread overview]
Message-ID: <16fd1f9d-e8a5-0caf-c262-80ef8e6d1891@gmail.com> (raw)
In-Reply-To: <e9a447d9-da58-87ac-3136-d1dc0c75d591@gmail.com>

W dniu 07.01.2017 o 00:45, Marek Vasut pisze:
> On 01/06/2017 06:19 PM, Marcin Krzeminski wrote:
>> Currently it is possible to disable chip erase for spi-nor driver.
>> Some modern stacked (multi die) flash chips do not support chip
>> erase opcode at all but spi-nor framework needs to cope with them too.
>> This commit extends existing functionality to allow disable
>> chip erase for a single flash chip.
> I wonder whether this should really be opt-out flag. Since we'll see
> more multi-die chips (and chips with different die sizes), I'd say this
> should rather be opt-in flag.
Multi-die does not mean that chip will not support chip erase (we have 
already a multi-die
chips that still do chip erase). Please think about this patch more like 
a bug-fix not a feature.
More likely this will be flag kinda similar to eg. USE_FSR - for some 
manufacturers only.

We are far away for real die erase functionality in spi-nor framework 
(due to 4byte mode bootloaders issue).
Die erase could be covered in different series -  maybe with more advanced
erase procedure that takes biggest available erase size?

Thanks,
Marcin
>
>> Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com>
>> ---
>>   drivers/mtd/spi-nor/spi-nor.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index 2a643a1..595de54 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -85,6 +85,7 @@ struct flash_info {
>>   					 * Use dedicated 4byte address op codes
>>   					 * to support memory size above 128Mib.
>>   					 */
>> +#define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
>>   };
>>   
>>   #define JEDEC_MFR(info)	((info)->id[0])
>> @@ -1621,6 +1622,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
>>   		nor->flags |= SNOR_F_USE_FSR;
>>   	if (info->flags & SPI_NOR_HAS_TB)
>>   		nor->flags |= SNOR_F_HAS_SR_TB;
>> +	if (info->flags & NO_CHIP_ERASE)
>> +		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
>>   
>>   #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
>>   	/* prefer "small sector" erase if possible */
>>
>

  reply	other threads:[~2017-01-07 22:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-06 17:18 [PATCH v4 0/2] mtd: spi-nor: Add possibility to disable chip erase Marcin Krzeminski
2017-01-06 17:19 ` [PATCH v4 1/2] mtd: spi-nor: Fix whole chip erasing for stacked chips Marcin Krzeminski
2017-01-06 23:45   ` Marek Vasut
2017-01-07 22:33     ` mar.krzeminski [this message]
2017-01-10 17:24     ` Cyrille Pitchen
2017-01-10 17:44       ` Marek Vasut
2017-01-11 11:03         ` Cyrille Pitchen
2017-01-11 13:07           ` Marek Vasut
2017-01-06 17:19 ` [PATCH v4 2/2] mtd: spi-nor: Disable chip erase for Micron n25q00 Marcin Krzeminski
2017-03-22 21:00 ` [PATCH v4 0/2] mtd: spi-nor: Add possibility to disable chip erase Cyrille Pitchen

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