Re: [PATCH 3/3][v3] mtd: nand: davinci: set ECC algorithm explicitly for HW based ECC

[Boris Brezillon <boris.brezillon@free-electrons.com>]

On Tue, 2 May 2017 11:00:45 +0200
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> On Tue,  2 May 2017 10:13:23 +0200
> Alexander Couzens <lynxis@fe80.eu> wrote:
> 
> > Required to set the ooblayout based on the algorithm.  
> 
> Not strictly required if you take my comment into account (see my
> reply to patch 2). This being said, it's always to have this kind of
> information, I'll just have to check if it doesn't conflict with
> Masahiro's patches.

Never mind, I'm just mixing up davinci and denali :-).

> 
> > 
> > Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
> > ---
> >  drivers/mtd/nand/davinci_nand.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
> > index 27fa8b87cd5f..9e5167496ce1 100644
> > --- a/drivers/mtd/nand/davinci_nand.c
> > +++ b/drivers/mtd/nand/davinci_nand.c
> > @@ -760,11 +760,13 @@ static int nand_davinci_probe(struct platform_device *pdev)
> >  			info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
> >  			info->chip.ecc.bytes = 10;
> >  			info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
> > -		} else {
> > +			info->chip.ecc.algo = NAND_ECC_BCH;
> > +		} else { /* 1bit ecc hamming */  
> 
> Please put this comment on the next line.
> 
> >  			info->chip.ecc.calculate = nand_davinci_calculate_1bit;
> >  			info->chip.ecc.correct = nand_davinci_correct_1bit;
> >  			info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
> >  			info->chip.ecc.bytes = 3;
> > +			info->chip.ecc.algo = NAND_ECC_HAMMING;
> >  		}
> >  		info->chip.ecc.size = 512;
> >  		info->chip.ecc.strength = pdata->ecc_bits;  
>