From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-mtd@lists.infradead.org, richard@nod.at,
dwmw2@infradead.org, computersforpeace@gmail.com,
marek.vasut@gmail.com, cyrille.pitchen@wedev4u.fr
Subject: Re: [PATCH] mtd: nand: hynix: add support for 20nm NAND chips
Date: Sun, 13 Aug 2017 09:50:35 +0200 [thread overview]
Message-ID: <20170813095035.6c4fc69e@bbrezillon> (raw)
In-Reply-To: <20170805121624.25553-1-martin.blumenstingl@googlemail.com>
Hi Martin,
Le Sat, 5 Aug 2017 14:16:24 +0200,
Martin Blumenstingl <martin.blumenstingl@googlemail.com> a écrit :
> According to the datasheet of the H27UCG8T2BTR the NAND Technology field
> (6th byte of the "Device Identifier Description", bits 0-2) the
> following values are possible:
> - 0x0 = 48nm
> - 0x1 = 41nm
> - 0x2 = 32nm
> - 0x3 = 26nm
> - 0x4 = 20nm
> - (all others are reserved)
>
> Fix this by extending the mask for this field to allow detecting value
> 0x4 (20nm) as valid NAND technology.
> Without this the detection of the ECC requirements fails, because the
> code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and
> aborts with "Invalid ECC requirements" because it cannot map the "ECC
> Level". Extending the mask makes the ECC requirement detection code
> recognize this chip as <= 26nm and sets up the ECC step size and ECC
> strength correctly.
Applied.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/mtd/nand/nand_hynix.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/nand_hynix.c b/drivers/mtd/nand/nand_hynix.c
> index b12dc7325378..bd9a6e343848 100644
> --- a/drivers/mtd/nand/nand_hynix.c
> +++ b/drivers/mtd/nand/nand_hynix.c
> @@ -477,7 +477,7 @@ static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
> * The ECC requirements field meaning depends on the
> * NAND technology.
> */
> - u8 nand_tech = chip->id.data[5] & 0x3;
> + u8 nand_tech = chip->id.data[5] & 0x7;
We should probably define macros to extract information from ID bytes
at some point, but let's keep that for later.
>
> if (nand_tech < 3) {
> /* > 26nm, reference: H27UBG8T2A datasheet */
> @@ -533,7 +533,7 @@ static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
> if (nand_tech > 0)
> chip->options |= NAND_NEED_SCRAMBLING;
> } else {
> - nand_tech = chip->id.data[5] & 0x3;
> + nand_tech = chip->id.data[5] & 0x7;
>
> /* < 32nm */
> if (nand_tech > 2)
prev parent reply other threads:[~2017-08-13 7:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-05 12:16 [PATCH] mtd: nand: hynix: add support for 20nm NAND chips Martin Blumenstingl
2017-08-13 7:50 ` Boris Brezillon [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170813095035.6c4fc69e@bbrezillon \
--to=boris.brezillon@free-electrons.com \
--cc=computersforpeace@gmail.com \
--cc=cyrille.pitchen@wedev4u.fr \
--cc=dwmw2@infradead.org \
--cc=linux-mtd@lists.infradead.org \
--cc=marek.vasut@gmail.com \
--cc=martin.blumenstingl@googlemail.com \
--cc=richard@nod.at \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox