[PATCH] mtd: nand: hynix: add support for 20nm NAND chips

[PATCH] mtd: nand: hynix: add support for 20nm NAND chips

[Martin Blumenstingl]

According to the datasheet of the H27UCG8T2BTR the NAND Technology field
(6th byte of the "Device Identifier Description", bits 0-2) the
following values are possible:
- 0x0 = 48nm
- 0x1 = 41nm
- 0x2 = 32nm
- 0x3 = 26nm
- 0x4 = 20nm
- (all others are reserved)

Fix this by extending the mask for this field to allow detecting value
0x4 (20nm) as valid NAND technology.
Without this the detection of the ECC requirements fails, because the
code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and
aborts with "Invalid ECC requirements" because it cannot map the "ECC
Level". Extending the mask makes the ECC requirement detection code
recognize this chip as <= 26nm and sets up the ECC step size and ECC
strength correctly.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/mtd/nand/nand_hynix.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_hynix.c b/drivers/mtd/nand/nand_hynix.c
index b12dc7325378..bd9a6e343848 100644
--- a/drivers/mtd/nand/nand_hynix.c
+++ b/drivers/mtd/nand/nand_hynix.c
@@ -477,7 +477,7 @@ static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
 		 * The ECC requirements field meaning depends on the
 		 * NAND technology.
 		 */
-		u8 nand_tech = chip->id.data[5] & 0x3;
+		u8 nand_tech = chip->id.data[5] & 0x7;
 
 		if (nand_tech < 3) {
 			/* > 26nm, reference: H27UBG8T2A datasheet */
@@ -533,7 +533,7 @@ static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
 		if (nand_tech > 0)
 			chip->options |= NAND_NEED_SCRAMBLING;
 	} else {
-		nand_tech = chip->id.data[5] & 0x3;
+		nand_tech = chip->id.data[5] & 0x7;
 
 		/* < 32nm */
 		if (nand_tech > 2)
-- 
2.13.4

Re: [PATCH] mtd: nand: hynix: add support for 20nm NAND chips

[Boris Brezillon]

Hi Martin,

Le Sat,  5 Aug 2017 14:16:24 +0200,
Martin Blumenstingl <martin.blumenstingl@googlemail.com> a écrit :

> According to the datasheet of the H27UCG8T2BTR the NAND Technology field
> (6th byte of the "Device Identifier Description", bits 0-2) the
> following values are possible:
> - 0x0 = 48nm
> - 0x1 = 41nm
> - 0x2 = 32nm
> - 0x3 = 26nm
> - 0x4 = 20nm
> - (all others are reserved)
> 
> Fix this by extending the mask for this field to allow detecting value
> 0x4 (20nm) as valid NAND technology.
> Without this the detection of the ECC requirements fails, because the
> code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and
> aborts with "Invalid ECC requirements" because it cannot map the "ECC
> Level". Extending the mask makes the ECC requirement detection code
> recognize this chip as <= 26nm and sets up the ECC step size and ECC
> strength correctly.

Applied.

> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/mtd/nand/nand_hynix.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand_hynix.c b/drivers/mtd/nand/nand_hynix.c
> index b12dc7325378..bd9a6e343848 100644
> --- a/drivers/mtd/nand/nand_hynix.c
> +++ b/drivers/mtd/nand/nand_hynix.c
> @@ -477,7 +477,7 @@ static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
>  		 * The ECC requirements field meaning depends on the
>  		 * NAND technology.
>  		 */
> -		u8 nand_tech = chip->id.data[5] & 0x3;
> +		u8 nand_tech = chip->id.data[5] & 0x7;

We should probably define macros to extract information from ID bytes
at some point, but let's keep that for later.

>  
>  		if (nand_tech < 3) {
>  			/* > 26nm, reference: H27UBG8T2A datasheet */
> @@ -533,7 +533,7 @@ static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
>  		if (nand_tech > 0)
>  			chip->options |= NAND_NEED_SCRAMBLING;
>  	} else {
> -		nand_tech = chip->id.data[5] & 0x3;
> +		nand_tech = chip->id.data[5] & 0x7;
>  
>  		/* < 32nm */
>  		if (nand_tech > 2)