* [PATCH v2] mtd: nand: samsung: add ECC requirements for K9F4G08U0D
@ 2017-12-07 9:33 Miquel Raynal
2017-12-07 20:22 ` Boris Brezillon
0 siblings, 1 reply; 2+ messages in thread
From: Miquel Raynal @ 2017-12-07 9:33 UTC (permalink / raw)
To: Boris Brezillon, Richard Weinberger, David Woodhouse,
Brian Norris, Marek Vasut, Cyrille Pitchen
Cc: linux-mtd, Miquel Raynal
Samsung NAND chip K9F4G08U0D minimum ECC strength requirement is 1 bit
per 512 bytes. As the chip is not ONFI nor JEDEC and because of the lack
of these values, boards using it fail to probe the NAND controller
driver. Fix this by setting up the default values.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
---
Changes since v1:
- Added the chip reference in the commit title
- Removed unnecessary checks.
drivers/mtd/nand/nand_samsung.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/nand/nand_samsung.c b/drivers/mtd/nand/nand_samsung.c
index d348f0129ae7..f6b0a63a068c 100644
--- a/drivers/mtd/nand/nand_samsung.c
+++ b/drivers/mtd/nand/nand_samsung.c
@@ -91,6 +91,12 @@ static void samsung_nand_decode_id(struct nand_chip *chip)
}
} else {
nand_decode_ext_id(chip);
+
+ /* Datasheet values for SLC Samsung K9F4G08U0D-S[I|C]B0(T00) */
+ if (nand_is_slc(chip) && chip->id.data[1] == 0xDC) {
+ chip->ecc_step_ds = 512;
+ chip->ecc_strength_ds = 1;
+ }
}
}
--
2.11.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] mtd: nand: samsung: add ECC requirements for K9F4G08U0D
2017-12-07 9:33 [PATCH v2] mtd: nand: samsung: add ECC requirements for K9F4G08U0D Miquel Raynal
@ 2017-12-07 20:22 ` Boris Brezillon
0 siblings, 0 replies; 2+ messages in thread
From: Boris Brezillon @ 2017-12-07 20:22 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, David Woodhouse, Brian Norris, Marek Vasut,
Cyrille Pitchen, linux-mtd
On Thu, 7 Dec 2017 10:33:58 +0100
Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
> Samsung NAND chip K9F4G08U0D minimum ECC strength requirement is 1 bit
> per 512 bytes. As the chip is not ONFI nor JEDEC and because of the lack
> of these values, boards using it fail to probe the NAND controller
> driver. Fix this by setting up the default values.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Applied.
Thanks,
Boris
> ---
>
> Changes since v1:
> - Added the chip reference in the commit title
> - Removed unnecessary checks.
>
> drivers/mtd/nand/nand_samsung.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mtd/nand/nand_samsung.c b/drivers/mtd/nand/nand_samsung.c
> index d348f0129ae7..f6b0a63a068c 100644
> --- a/drivers/mtd/nand/nand_samsung.c
> +++ b/drivers/mtd/nand/nand_samsung.c
> @@ -91,6 +91,12 @@ static void samsung_nand_decode_id(struct nand_chip *chip)
> }
> } else {
> nand_decode_ext_id(chip);
> +
> + /* Datasheet values for SLC Samsung K9F4G08U0D-S[I|C]B0(T00) */
> + if (nand_is_slc(chip) && chip->id.data[1] == 0xDC) {
> + chip->ecc_step_ds = 512;
> + chip->ecc_strength_ds = 1;
> + }
> }
> }
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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